Improved Power Management with Sonics’ ICE-Grain

Compared to conventional, software controlled approaches, Sonics’ fine-grain hardware-controlled state transitions enable the architecture to exploit many more “off” and low-power states.

It was not long ago that the issue of Low Power was handled as an exception by the EDA industry. Today every electronic circuit designers must minimize power consumption, although the reasons for such requirement may vary. Battery life, thermal management, energy conservation due to economic factors, regulatory concerns like Energy Star from the U.S. Department of Energy, remote execution environments like space or under oceans, are some of the reasons to minimize power consumption.

EDA vendors provide power analysis tools as well as power aware development like synthesis, place and route tools, but it has been shown by many academic papers that the best results are obtained at the architectural level. At that point designers have a better sense of what can be either shutdown or taken to a slower state of execution.

The Power Management Challenge
Designer must worry about both active power and leakage power. Engineers address the problem from a functional point of view by segmenting the circuit into domains dedicated to the execution of functions that are somewhat independent from each other. Figure 1 shows the most popular techniques for power management together with the execution latency, that is the time it takes to transition from normal operation state to power saving state. Latency can vary with each technique from few nanoseconds to over a millisecond. Latency can render the technique ineffective, especially when the execution latency is approximately as long as the available idle time.

Figure 1. The most popular techniques for power management are shown, together with the execution latency.

There is a tradeoff between techniques when working on dynamic power management. Sonics has been working on this issue with its customers and recognized the challenges involved. In general one has to figure out when the block is idle, the idle time has to be long enough to cover the transition latency because otherwise one can run into power state trashing that not only does not save power, but uses more power because it uses power to change states.

Different tasks must be accomplish in designing and developing a power saving strategy.

  • Identify and exploit idle moments long enough to cover the latency.
  • Select optimum power domain boundaries.
  • Avoid deadlock due to domain hierarchies and interdependencies.
  • Choose the appropriate techniques for power control for each domain.

There are significant challenges with each of the above tasks.

  • Avoid power state thrashing
  • Scaling voltage and frequency to match loading and thermal limits
  • Finer domains offer more savings, but demand bigger implementation cost
  • Define how many power state transitions per second can be handled

Verification is of course a major challenge. Designers need not only to verify power control circuitry correctness, especially absence of deadlock states, but also must evaluate the effectiveness of dynamic power control.

The Ice-Grain Solution
Because current power management solutions either fall short or are complex to implement and verify,. Sonics is attacking power management holistically to create the industry’s most effective solution. The company has created The ICE-Grain Power Architecture that saves far more power than ad hoc power management approaches. It is a complete power management subsystem consisting of hardware and software IP that manages clock and power control, external voltage sources, operating points for DVFS, and others techniques providing an easy to use, unified, and automated solution.

With the ICE-Grain Power Architecture, SoC designers partition their chips into much finer “grains,” which enables up to 10x faster and more precise power control. Power “grains” are very small sections of an SoC that include functional logic that can be individually power controlled using one or more savings methods. A grain is connected to one or more clock domains and attached to at least one power domain, and includes defined signals and conditions for power control. Grains are often an order of magnitude smaller than conventionally independent power or clocking domains, and multiple grains can be composed into larger hierarchical grains. The ICE-Grain Power Architecture automates the tasks of grain connection and management by synthesizing both central and local control circuitry blocks for the greatest total SoC power reduction (Figure 2).

Figure 2. Representation of an SoC partitioned into many Power Grains with a power controller synthesized to simultaneously control each grain. The zoomed view shows the local control element on each grain – highlighting the modular and distributed construction of the ICE-Grain architecture.

The ICE-Grain architecture is scalable and modular, to fit all design requirements. Each grain has its own local independent tightly coupled controller. For example, if a number of grains are power switched from the same external supply, then this supply cannot be turned off unless all of the grains are able to power down. For this reason the associated local controllers must be tightly coupled with a Central Controller that manages the shared resource. A voltage supply, the output of a phase lock loop, the interface to a software based power management system are all examples of a shared resource. The Central Controller distributes the job of controlling every grain to Local Grain Controllers. This architecture allows ICE-Grain to support a highly scalable number of grains autonomously without imposing any loading on the host CPU – but will interface to the host to take power directives from the hardware or operating system. For example, the host CPU may tell the Central Controller to change system state from “Awake” to “Doze”, and then Sonics-provided drivers will program the Central Controller to determine all of the legal power states that each Local Grain Controller can exploit to achieve the lowest power state (Figure 3).

Figure 3. Architecture of Central Controller and associated Local Grain Controllers.

The ICE-Grain Power Architecture leverages but is independent of the SonicsGN configurable On-chip Network that provides a high-performance network for the transportation of packetized data, utilizing routers as the fundamental switching elements. The ICE-Grain Power Architecture automates the tasks of grain connection and management by analyzing every grain and then, synthesizing both central and local control circuitry blocks for the greatest total SoC power reduction.

Advantages Over Conventional Approaches
Compared to conventional, software-controlled approaches, Sonics’ scalable architecture helps designers partition their designs into much smaller power grains, providing many more opportunities to turn individual grains to the “off” state. Its hardware-controlled state transitions enable the architecture to exploit shorter idle periods by reducing the execution latency so power grains can be taken to deeper “off” and low-power states than can be achieved using software-controlled approaches.

ICE-Grain is a scalable, distributed, and modular architecture that provides the most efficient power management precisely where it is needed. It is the first commercial technology that manages and controls all common power techniques in a unified environment. It does so while complying with standard EDA tools, flows, and formats.

To developers ICE-Grain provides a complete, integrated solution that does not require any special power expertise. The result is an easy to use, worry-free implementation of hardware control and fine grain power reduction.

ICE-Grain saves power in three main ways: enable designers to reliably create very fine-grained power objects, execute power state transitions in hardware that is up to 10x faster than software, and finally utilize a “wake on demand” technique that detects when a grain that has been powered down needs to wake up – and does so automatically.

Figure 4 shows a comparison between the result of a software driven power management system and what ICE-Grain will achieve. The dark green area represent a locality on the SoC that can be idle for a certain length of time at a specific execution point. Total power will be saved by taking this hardware to a lower power state. To get to the lower power state using a software controlled technique the host processor needs to execute a sequence of functions. During that time no power is saved in fact extra power is consumed by the required processing. When the hardware that had been taken to the lower state must resume normal execution, another sequence of functions, again requiring additional power must be performed. In the example shown, the CPU-based system will consume more energy entering and exiting the low-power state than is saved in the low-power state itself.

Figure 4. ICE-Grain hardware-controlled state transitions are far faster and lower-power than CPU-based power managers.

In contrast, the ICE-Grain switching occurs in hardware and does not involve the host processor. So both the time it takes to transition and the amount of power needed to effect the transition in either direction is far less, as shown by the light green areas representing additional power savings compared to the CPU-based controller. In this example, expending the energy to enter and exit the low-power state will lower overall system power. Thus, ICE-Grain can save power over conventional approaches in all cases and can exploit idle regions too short for conventional approaches to save additional power.

The history of the electronics industry offers a number of instances where software techniques used early to achieve specific targets are later replaced with hardware based technology that yields more efficient results.

Compared to conventional, software controlled approaches, Sonics’ fine-grain hardware-controlled state transitions enable the architecture to exploit many more “off” and low-power states. The idea of minimizing the size of the block controlled is key because it allows designers to ignore other regions of the larger block with logic states that would otherwise inhibit the application of power management to the smaller hardware region. Controlling smaller blocks like the grains in the ICE-Grain architecture would require such large overhead in software to make it impossible to apply.

Share and Enjoy:
  • Digg
  • Sphinn
  • Facebook
  • Mixx
  • Google
  • TwitThis