The Odd Couple – Analog IPs and Design Data Management
Design engineers used to call mixed-signal chips “big D/little A” for their high digital content paired with a small analog portion. However, the balance of power is changing with the emergence of new technologies such as the Internet of Things (IoT), automotive, bio-tech, etc., where a growing number of sensors and actuators are interfacing with the real world.
This is a glimpse into the future, where sensors are like the magical sriracha sauce, accompanied by multiple analog pieces, while in many cases the digital part comes as a prepackaged subsystem. Now, just as these new groundbreaking technologies are about to take off, there is growing recognition of the dearth of talented and experienced analog engineers, a resource conundrum often called “analog’s day of reckoning.”
Figure 1: Figure 1: IoT is shifting the SoC design balance toward analog (Source: ARM Ltd.)
It is therefore no surprise that the analog design cycle is going through profound changes just as the semiconductor industry is hard at work on how to speed up the system-on-chip (SoC) development cycle. Even as high-performance analog continues to rely on the full custom process, there are a significant number of analog design use-cases where design integrators can leverage existing analog designs. Given the mantra these days of “IP reuse,” and given the paucity of analog designers, chipmakers are increasingly relying on reuse of internal IPs as well as off-the-shelf IP products from different sources.
Analog IPs are typically “hard” IPs. Once an analog IP has been developed, for re-use it has to be mapped to the desired process node and tested. This has led to a growing number of analog IP companies that are catering to the demands of semiconductor design companies by developing standard analog IPs and mapping them to the desired process nodes. Take IQ-Analog Corp., for instance, an IP company that offers IPs such as A/D or D/A data converters with proven silicon performance for multiple foundries and different process nodes. The mere existence of outfits like IQ-Analog is testament to the departure by design companies from full-custom analog design and their willingness to leverage existing IPs.
Figure 2: Form to search IQ-Analog IP database (Source: IQ-Analog)
Industry pundits predict that the mixed-signal design environment of the future will be a heterogeneous design environment in which custom design and off-the-shelf analog IP go hand in hand, along with digital and RF modules, as design companies vie for differentiation while trying to meet their tight design schedules. The emergence of new process technologies such as “two-and-half-D” or “3-D” technologies will facilitate analog IPs reuse in existing process nodes.
However, the use of analog IPs doesn’t come without challenges. The process of mapping analog IPs to different process nodes in different foundries requires managing a lot of design data and process design kits (PDKs). Once the IPs are mapped to the desired process node, they need to be verified and integrated into the SoCs with the required data converters to ensure that they work as intended. To ensure easy migration, companies such as IQ-Analog have come up with their methodologies using data management tools to map functionally-verified analog IPs to different process nodes for a specific foundry. Moreover, the growing reliance on design reuse and third-party IP leads to a number of challenges in merging data from different sources. Tracking the data and ensuring its consistency across the entire SoC value chain becomes a daunting task when design teams are large and are located at geographically-dispersed design sites.
Figure 3: Traditional design flows lead to delays in SoC turnarounds (Source: CERN)(Source: IQ-Analog)
Multiple sites bring another design challenge. While creating analog designs, designers can accidentally overwrite each other’s changes, and their libraries become cluttered with unwanted cells and versions. Verification work takes a lot of time and effort, and moving to smaller nodes means that there will be more verification work across wider variations. Design engineers need to pick changes from numerous lines of development even as changes take place on multiple axes. Unlike in digital design, where it is relatively easier to identify changes by doing a ‘diff’ in Unix, with analog design it is quite difficult to identify changes made to either the design or to the properties of the cells. In the absence of a comprehensive data management system, designers often consider the simulation results suspect, as they are not sure whether anyone has modified the design.
With the desire to have their design differentiated, as well as to meet their SoC timelines and leverage their analog IPs, design companies have slowly realized that what works in the digital environment does not necessarily work in the analog design space. For analog/mixed-signal designs, it is increasingly important to used specialized design data management systems that are integrated with EDA tools to keep track of the various versions of the analog IPs, library cells, PDKs, schematics, layouts, project configurations, etc. The use of a data management system brings along with it automation that allows designers to establish a seamless project configuration and thus efficiently leverage their ever-growing library of IP content without any redundancies. Such a system also mitigates the risk of errors that can inadvertently be introduced while mapping an analog IP from one process node to another.
The specific nature of analog/mixed-signal designs requires that the design data management tool is aware of the unique analog data structure. The data management systems typically used for digital designs are the ones that are commonly targeted for the software development environment. While tools such as Subversion or Git can deal with front-end digital design data, usually comprised of textual HDL code like Verilog/VHDL, design objects in the analog domain deal with schematics and layout, which are represented as binary data. Identifying differences between two versions of the schematic or layout requires an understanding of the data structure of the tool used to create the schematic.
Since implementation of analog/ mixed-signal designs is unique, design data management tools must also be integrated with analog/mixed-signal EDA tools such as Cadence® Virtuoso®, Keysight Technologies’ Advanced Design System (ADS), Mentor Graphics Pyxis, and Synopsys Galaxy Custom Designer® and Laker3™ Custom Design. While there are many software-based data management systems such as Perforce, Subversion etc., they lack the integration needed for managing analog/mixed-signal designs. Moreover with the number of RF modules continuing to grow in SoCs, it becomes important to use a data management tool which meets all types of designs: digital, analog, mixed-signal and RF. ClioSoft’s SOS design data management platform is the only true hardware-based data management system that provides integration with analog/RF/digital tools from all major EDA vendors.
Many design companies use the Cadence Virtuoso platform for analog designs, including the world-renowned European research institute, CERN, which carries out collaborative design work with 70 to 120 chip designers from 20 to 30 universities and research institutes. CERN uses ClioSoft’s SOS design management platform for managing analog/mixed-signal designs to achieve optimum use of resources among different sites. The SOS platform provides designers at all sites access to design data and changes in real time, and thus frees them from the periodic synchs and artificial partitioning common to SoC designs.
Alternatively, some design companies involved with analog/mixed-signal designs use the Synopsys tools (Laker or Custom Designer). For example, Dortmund, Germany-based Elmos Semiconductor AG, specializing in mixed-signal designs for the automotive industry, uses Synopsys Custom Designer along with ClioSoft’s SOS data management system to manage different versions of cells, libraries and cell views and to establish a seamless project configuration so that all designers can use the same versions of the design data.
Some design companies prefer to keep the data management systems unique to the analog/ mixed-signal design groups and digital groups separate. However, with the growing use of analog designs in today’s SoCs, design managers are realizing the inefficiencies of keeping two separate data management systems and are slowly but surely migrating to a single design data management system best suited to handle the unique requirements of the analog designs. For example, INVECAS Inc., a global digital and mixed-signal IP provider for Global Foundries, with teams in California, Vermont and in India, uses ClioSoft’s SOS data management system as a company-wide revision tool. SOS’s distributed architecture and decentralized tool management allows its engineering groups at different sites to quickly adapt and manage their IP design flows. SOS’s ability to reference and reuse existing IPs developed by remote design teams helps INVECAS build those IPs into their next generation SoCs.
SoC design teams will continue to get larger and will grow at different geographical locations where the required talent is available. With the increase in the number of design sites, managing data access, prevention of data loss and easy recovery from errors becomes all the more important. Given that design companies are inclined to use best-in-class tools from different tool vendors, managing the design data as well as the design handoff between the different team members becomes important. There was a time during the “big D/little A” days where a design data management tool was considered a nice-to-have. However, with the tables turned and analog/mixed-signal designs ruling the roost, a design data management tool designed specifically to handle the challenges of digital/analog/RF/mixed-signal designs to facilitate a multi-site collaboration environment for design teams becomes an absolute necessity. More so in this era of near-impossible design schedules.
About the Author:
Ranjit Adhikary, director of marketing at ClioSoft Inc., has 15 years experience in EDA engineering and technical and product marketing.
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