Second DVCon India Kicks Off Soon

By Thomas L. Anderson, Vice President of Marketing, Breker Verification Systems, Inc.

Last year the longtime USA-based Design and Verification Conference and Exhibition (DVCon) expanded to India for the first time. The debut DVCon India event was a major hit, drawing more than 450 attendees from more than 80 different companies and universities. This year’s event will build on that success for an even bigger and better show, September 10-11 in Bangalore’s stunning Leela Palace hotel.

The full program is available online at Again this year, the program is divided into two tracks: electronic system level (ESL) and design and verification (DV). Both tracks feature keynote speeches by industry experts, lively and topical panels, in-depth tutorials, and technical presentations from working engineers. The focus for DVCon India is on practical solutions to design and verification problems rather than on esoteric academic visions.

The keynote speakers include executives from Synopsys, Mentor, Infineon, and other leading companies in the electronics industry. The three panels focus on topics sure to encourage audience participation: the Internet-of-things (IoT), new verification flows, and the ESL continuum. These sessions span both days, some open to the whole conference and some in one of the tracks. Attendees are encouraged to switch between the two tracks to attend whatever sessions are of interest.

The first day’s focus is on tutorials, with a total of eleven diverse subjects covered in an in-depth classroom setting. These include early architectural exploration, creating simulation testbenches, leveraging portable stimulus across platforms, expediting code coverage, using software-driven verification, system-on-chip (SoC) debug, and FPGA prototyping. All tutorials offer real-world design and verification techniques that can be applied by attendees “back at the office.”

The range of topics covered by nearly 40 technical paper sessions on the second day is even broader. The DV track includes many aspects of verification, including simulation, acceleration, stimulus generation, graph-based techniques, formal and static methods, coverage closure, performance measurement, and analog/mixed-signal (AMS) verification. The ESL track focuses on system-level modeling and validation of processors, systems, algorithms, and performance early in the development process. There are also a dozen poster presentations that echo many of these same topics.

One major theme that emerged last year was the critical importance of industry standards. Again this year, many of the tutorial and talks will address existing and emerging standards such as:

  • SystemC
  • Transaction-Level Modeling (TLM)
  • SystemVerilog
  • Universal Verification Methodology (UVM)
  • Verilog-AMS
  • VHDL
  • Open Source VHDL Verification Methodology (OS-VVM)
  • Portable Stimulus

On top of all the quality technical content, DVCon India will offer plenty of time for networking with colleagues and vendors. More than 30 sponsors will staff booths in an exhibition area, showing how many of the ideas discussed in the sessions can be used on projects today with the assistance of commercial solutions. The booths will be open through both days, with most activity occurring during lunch and tea-time breaks.

Thursday night, after the sessions conclude, all attendees are invited to a special gala dinner celebrating the tenth anniversary of the standardization of SystemVerilog as IEEE 1800-2005 and the recent transfer of the UVM from Accellera to the IEEE. The evening will also feature entertainment, so it will be a must-attend event. In truth, the whole conference is a must for anyone involved in the architecture, design, or verification of complex electronic systems.

Breker is proud to be a supporter of DVCon India again this year. We will present a joint tutorial on portable stimulus with Mentor Graphics and Vayavya, plus we will have a booth in the exhibition area. We urge you to attend this show, which is certain to be technically rich, personally rewarding, and downright enjoyable. For more information, or to register to attend, visit We‘ll see you in Bangalore!

About Thomas L. Anderson

Thomas L. Anderson is Co-Chair of the DVCon India Promotions Committee. He serves as vice president of marketing at Breker Verification Systems, the SoC Verification Company. He has more than a dozen years of experience in EDA verification applications and marketing, having served in increasing responsible roles at Cadence, Synopsys and 0-In Design Automation. Anderson holds a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst and a Master of Science degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology (MIT).

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