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The Changing (and Challenging) IC Reliability Landscape

By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics

It seems that a laser focus on integrated circuit (IC) reliability is all around us now. Gone are the days when a little “over design,” or additional design margin, could cover the reliability issues in a design layout. Designers now need to articulate to partners, both internal and external, just how well their designs function over time and within their intended environment.

Functional safety and the push from the automotive electronics industry with ISO 26262 are not the only realms where this critical focus is being applied. General consumer devices that are always on, manufactured in the 10s to 100s of millions, are seeking the benefit of eliminating reliability issues at the IC design stage. The broad interest being shown over a wide range of process nodes, from the largest, most-established nodes to the emerging “bleeding edge” nodes, demonstrate this shift in attitude about and consideration given to reliability issues.

Many IC designers and verification teams no longer consider the obvious DRC and LVS milestones as sufficient stopping points—they continue on to advanced reliability checks aimed at increasing the longevity, performance and quality of their designs. They have taken the proactive approach of looking “one layer deeper” towards quality to avoid these subtle design problems that will impact the lifetime operation of their products.

Earlier this year, I saw a great article on what some folks are doing on the modeling side by considering random telegraph noise (RTN), and its contribution to negative-bias temperature instability (NBTI) failures and device shifts in VT [1]. It reminded me of the work I was anticipating seeing at the 2015 International Reliability Physics Symposium (IRPS). With a focus on reliability, you’d expect advanced detection and verification topics to shine and garner great interest, and they did! The conference organizers also presented the Best Paper and Outstanding Paper awards from last year’s conference. A. Oates and M.-H. Lin from Taiwan Semiconductor Manufacturing Company (TSMC) took the honors for Best Paper with “Electromigration Failure of Circuit-Like Interconnects: Short Length Failure Time Distributions with Active Sinks and Reservoirs” [2]. For Outstanding Paper, it was the team from TU Wien and IMEC (T. Grasser, K. Rott, H. Reisinger, M. Waltl, J. Franco and B. Kaczer), that delivered “A Unified Perspective of RTN and BTI” [3]. This work evaluates the suggestion that RTN and bias temperature instability (BTI) are due to similar defects. Understanding the failure mode of these effects is critically important, especially when designing accelerated test procedures to create data. Stress the device in the “wrong” way, and maybe you’re not capturing the degradation effects you think you are.

Some reliability failure modes are more familiar to designers than others, just because you tend to hear about them more often, including electromigration (EM), electrical overstress (EOS), and electrostatic discharge (ESD). With standards now calling out effects like charged device model (CDM), hot carrier injection (HCI), NBTI, and others, IC designers and verification specialists are finding there’s a whole new set of acronyms to learn about and remember. Not familiar with these? Now is the time to study up. There is increasing pressure to have validated mitigation strategies for these effects in place for the physical design implementation stage.

What’s That Mean?

To help those of you new to this field, here’s a brief introduction to the effects I just mentioned. There are many, many great references out there, and I’d encourage you to start exploring reliability design and verification resources, if you’re not already. I’ve supplied a few at the end of this article that would make a good beginning library.

CDM is a model that characterizes the susceptibility of an electronic device to damage from ESD. The CDM model is an alternative to the human body model (HBM), which is built on the generation and discharge of electricity from (you guessed it) a human body. The CDM model simulates the build-up and discharge of electricity that occurs in other circumstances, like handling during the assembly and manufacturing process. Devices that are classified according to CDM are exposed to a charge at a standardized voltage level, and then tested for survival. If the device withstands this voltage level, it is tested at the next level, and so on, until the device fails. CDM is standardized by JEDEC in JESD22-C101E [4].

HCI is a phenomenon in solid-state electronic devices where an electron (or “hole”) gains sufficient kinetic energy to overcome a potential barrier and break an interface state. The term “hot” does not refer to the overall temperature of the device, but to the effective temperature used to model carrier density. The switching characteristics of the transistor can be permanently changed, as these charge carriers can become permanently trapped in the gate dielectric of a MOS transistor. As HCI degradation slows down circuit speeds, it is sometimes considered more of a performance problem than a reliability issue, despite potentially leading to operational failure of the circuit. [5] [6].

NBTI is a key reliability issue in MOSFETs that manifests as an increase in the threshold voltage. It also causes a decrease in drain current and transconductance of a MOSFET. This degradation exhibits logarithmic dependence on time. While NBTI is of immediate concern in p-channel MOS devices, since they almost always operate with negative gate-to-source voltage, the very same mechanism also affects nMOS transistors when biased in the accumulation regime (i.e., with a negative bias applied to the gate) [7]. In the past, designers had no effective means of detecting potential NBTI conditions, so often the only option was to design all parts of the chip to absolute worst-case corner conditions. Newer verification tools that can combine both geometrical and electrical data can now locate NBTI sensitivities.

There is a growing need to be familiar with these and other reliability concerns to meet the market requirements of today’s IC customers. Not to be caught resting on their laurels, however, the reliability experts are forging ahead on advanced reliability topics and techniques. One that caught my eye is an effort to develop a unified aging model of NBTI and HCI by leveraging the way degradation for both are modeled [8]. By employing a common reaction-diffusion (R-D) framework, a proposal for a geometry-dependent unified R-D model for NBTI and HCI has been proposed [9]. How well will it work? Can it be used to develop design constraints? These are still unanswered questions by many. I’m expecting that advances in this field will represent the next milestone of required checks that our devices will need to pass.

Some Final Thoughts

From a practical perspective, the difference between yield and reliability is when the failure occurs. Focus on yield issues has been at the forefront for a good many years, but it now seems that the industry is migrating to greater awareness on reliability issues. Tackling issues in this space requires an in-depth understanding of the physical layout and interactions that may be present. Of course, the guidance and creation of design rules for overcoming these issues is in the hands of the reliability experts, and the development of the tools that will help designers perform the analysis and mitigation is in the hands of the EDA vendors, but based on the research and activity presently underway, I feel confident that the future of reliability design and verification is headed in the right direction.

Reliability Resources

Understanding Automotive Reliability and ISO 26262 for Safety-Critical Systems

Physical Verification Flow for Hierarchical Analog IC Design Constraints

Reliability Characterisation of Electrical and Electronic Systems, Jonathan Swingler (Editor), ISBN:978-1782422211 (January 2015)

References

[1]   The End of Silicon?, Katherine Derbyshire, May 2015, http://semiengineering.com/the-end-of-silicon/

[2]   A. Oates and M.-H. Lin, “Electromigration Failure of Circuit-Like Interconnects: Short Length Failure Time Distributions with Active Sinks and Reservoirs”, IRPS 2014, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6860657

[3]   T. Grasser, K. Rott, H. Reisinger, M. Waltl, J. Franco and B. Kaczer, “A Unified Perspective of RTN and BTI”, IRPS 2014, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6860643

[4]   Charged-device model, https://en.wikipedia.org/wiki/Charged-device_model

[5]   Hot-carrier injection, https://en.wikipedia.org/wiki/Hot-carrier_injection

[6]   John Keane, Chris H. Kim, “Transistor Aging”, IEEE Spectrum, May 2011, http://spectrum.ieee.org/semiconductors/processors/transistor-aging/0

[7]   Negative-bias temperature instability, https://en.wikipedia.org/wiki/Negative-bias_temperature_instability

[8]   Yao Wang, Sorin Cotofana, Liang Fang , “A Unified Aging Model of NBTI and HCI Degradation towards Lifetime Reliability Management for Nanoscale MOSFET Circuits”, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5941501

[9]   H. Kufluoglu and M. Ashraful Alam, “A Geometrical Unification of the Theories of NBTI and HCI Time-exponents and its Implications for Ultra-scaled Planar and Surround-Gate MOSFETs,” in IEEE International Electron Devices Meeting, IEDM Technical Digest, Dec. 2004, pp. 113 – 116. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1419081

Author

Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of IIRW and the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at matthew_hogan@mentor.com.

Contact Information

Mentor Graphics – Veloce Emulation Platform

8005 SW Boeckman Rd.
Wilsonville, OR, 97070
USA

tele: 1-503-685-8000
toll-free: 1-800-547-3000
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