Cadence Allegro SiP and PVS Technologies Enabled for TSMC InFO Packaging Technology
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its Allegro® System-in-Package (SiP) and Physical Verification System (PVS) implementation technologies have been enabled for TSMC’s Integrated Fan-Out (InFO) packaging technology. By providing an integrated solution that automates the design-rule checking (DRC) flow, the Allegro SiP design tools and PVS enable TSMC customers to shorten the InFO design and verification cycle.
TSMC’s InFO advanced wafer-level packaging technology provides cost-effective system scaling to increase system bandwidth, while decreasing power consumption and device form factors. Compared to other methodologies, InFO is an ideal solution for mobile and Internet of Things (IoT) applications.
For more information on Allegro SiP tools and PVS solutions, visit www.cadence.com/news/InFO.
In collaborating with TSMC for this enablement, Cadence developed new IC packaging technology in Allegro SiP Layout to address InFO-specific design requirements, and provided features that allow designers to meet and verify the design rules, layout structures and metal density requirements of an InFO design. Cadence tailored the mask-generation technology to accurately represent the InFO design structures in GDSII, allowing designers to verify the accuracy of the mask prior to submission to TSMC for fabrication.
“As the demand for mobile and IoT applications grows, the need for advanced packaging options increases as well,” said Keith Felton, product management group director for the PCB Group at Cadence. “Our in-house expertise in IC Packaging design and IC Physical Verification coupled with our experience working with TSMC enables us to develop and deliver specific InFO layout and verification features to meet their manufacturing requirements in design, leading to shorter design cycles and faster time to market.”
“By working closely with us and our lead customers, Cadence was able to address the unique needs of InFO packaging and develop and validate a complete solution,” said Suk Lee, senior director of Design Infrastructure Marketing Division at TSMC. “This integrated tool flow bridges the domains of both IC package design and IC manufacturing, ultimately leading to our overall successful broad deployment of the InFO packaging technology.”
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.
Cadence Design Systems, Inc.2655 Seely Avenue
San Jose, CA, 95134