Mentor Graphics Tackles SoC Design Challenges
System-on-a-chip designs are complex endeavors, and they are growing more complicated by the day. Mentor Graphics is cognizant of the many challenges in SoC design and is working to ease the troubles of chip designers.
The electronic design automation software and services company was established in 1981, making it one of the oldest existing EDA suppliers in the industry. Walden C. (Wally) Rhines, Mentor’s chairman and chief executive officer, is being recognized next month with the annual Phil Kaufman Award, given by the EDA Consortium and the IEEE Council on EDA, for distinguished contributions to EDA.
Shankar Krishnamoorthy, Chief Scientist for Mentor’s IC Implementation Division, says there are three key elements to SoC design at present – register-transfer level design, implementation, and sign-off.
In RTL, “the biggest challenge is designs are getting so large and complex,” Krishnamoorthy says. Designers must take into account the performance, area, and power consumption of the full chip, he adds.
“SoCs are getting very large and complex – there are many decisions that are made at RTL stage that impact performance, power and area.”
Sudhakar Jilla, director of marketing for the Olympus-SoC and RealTime Designer products within the IC Implementation Division, says today designers have to do a bottom up approach of synthesizing each RTL module separately, implementing the physical partitions and then finally stitching it all up at the chip level to get an early estimate of the timing, power and area – this process is taking way too long, he notes.
“Wait four months – it’s too late,” Jilla says.
Semiconductor intellectual property is “developed in relative isolation, in multiple places,” Krishnamoorthy observes. “The quality for IPs needs to be changed significantly.”
In the IP qualification process, designers must consider physical implementation in addition to functional verification, according to Krishnamoorthy. “RTL Designer must be able identify congestion hotspots and design feasibility during RTL design. They should also consider the chip level context of the IP and explore the PPA tradeoffs early in the design cycle”
There is a movement afoot to get away from channel-based floorplans, opting for channel-less or channel-light floorplans, Krishnamoorthy adds.
In sign-off, there is “a very interesting phenomenon,” Krishnamoorthy says. “The number of corners is spiking up a lot.”
Jilla says SoC designs have gone from a typical six to eight corners to up to 20 corners. “The old problems have gotten worse,” he adds.
Krishnamoorthy observes, “Just because you finish your place-and-route, you’re not done.”
With coloring and other considerations in designing advanced SoCs, “the last mile has become longer,” Jilla says. “Place-and-route was two weeks. It’s now four to six weeks.”
Mentor Graphics is keeping up with “the leading edge of the lithography world,” Krishnamoorthy says. “All the leading foundries use Mentor tools. It gives us an idea of what the foundries are doing with lithography.”
Modern designs can call for two or three colors, and there is double-patterning and triple-patterning involved in immersion lithography, according to Krishnamoorthy. Working with the top foundries “really helps us get an early understanding of these challenges,” he says. “Ten nanometer is already here.”
And chips with 7-nanometer features are on the horizon for EDA companies, silicon foundries, and others. Mentor is working with leading foundries on 7nm IC design and manufacturing, according to Jilla. “Support for 7nm is underway,” he says.