Mentor Graphics Veloce VirtuaLAB Adds Next-Generation Protocols for Leading-edge Networking Designs
Mentor Graphics Corp. today announced the Veloce® VirtuaLAB Ethernet environment with support for 25G, 50G and 100G Ethernet. This support enables highly efficient, emulation-based verification for the massive Ethernet-based designs being created today.
The huge surge in demand for connectivity has had a profound effect on the size of switch and router designs, making them among the largest IC designs developed today. The sheer size of the designs, the pressure for early release, and the need to verify all paths are creating a methodology shift that moves verification from simulation- to emulation-based flows.
“Providing a highly scalable, high-density network foundation for our customers’ demanding environments is a top priority as we design Juniper Networks’ advanced switches and routers,” said Debashis Basu, senior vice president of Silicon and Systems Engineering at Juniper Networks. “The cutting-edge features in our ASICs make Veloce VirtuaLAB Ethernet and emulation capabilities a key component for achieving verification convergence, helping ensure that we deliver versatile, high-performance switching and routing technology to keep pace with evolving network requirements.”
VirtuaLAB Ethernet transforms emulation for networking chips by replacing the traditional physical devices used in In-circuit Emulation (ICE) with virtual devices. This virtualization moves emulation from the engineering lab to the computing data center for maximum emulation resource utilization. “It’s a solution to Ethernet lab virtualization. That’s a very big pain point for our networking customers. We’re addressing it very efficiently with the VirtualLAB Ethernet,” said Jean-Marie Brunet, Marketing Director for the Emulation Division at Mentor Graphics Corp.
VirtuaLAB components provide a complete software-driven Ethernet stack that runs at up to 15,000 times the speed of traditional simulation. This lets VirtuaLab Ethernet users tackle the complex challenges of Ethernet-based designs with improved throughput, advanced debug, power analysis and performance analysis.
“The rapid development and deployment of high-end Ethernet products for the networking market requires access to high quality IP and complete verification solutions,” said Daniel Kohler, CTO of MoreThanIP. “We have collaborated with Mentor over several years to enable the deployment of robust, fully featured Ethernet verification encapsulated in the Ethernet VirtuaLAB product. Most recently we have collaborated to enable forward error correction (FEC) verification for high-speed 25G, 50G, 100G designs.”
According to the 2015 Ethernet Roadmap developed by the Ethernet Alliance Organization, Ethernet could have 12 speeds before 2020 with 6 new speeds introduced in the next 5 years. The progression of speeds is not in chronological order because 40G and 100G were primarily based on multiple lanes of 10Gb/s technology that was available before 25Gb/s serial technology enabled 25G. Lanes running at 25Gb/s are becoming impractical in 2015 and will be used in 25G SFP+ and 4×25Gb/s 100G QSFP28. The next serial lane is expected to be 50 Gb/s and enable 50G SFP28, 200G QSFP28 (4×50G) and 400G CFP2 (8×50G).
“It’s starting to be a little bit all over the place,” said Brunet. “That’s the reason why we had to expand our portfolio and support different protocols of Ethernet speed.”
The need for bandwidth is driven in different ways by data centers, cloud computing, metro area networks, storage area networks, social networking and video applications. “Video (for example) is driving the need for high bandwidth, fast computation (or the exchange of packets of information),” said Brunet.
The accelerated deployment of VirtuaLab solutions in the networking market is the result of significant and repeatable improvements in throughput. For example, in simulation it’s not uncommon to run 1,000 packets of data per day. When compared to emulation, the difference is staggering. Here customers report they are running 11,000,000 packets of data per day.
“We collaborate with leading-edge networking companies to provide solutions that address their verification challenges. The rapid growth of these designs and the need to verify every path creates a huge verification space resulting in a major shift from simulation to emulation,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “We developed VirtuaLAB Ethernet and other solutions that transform emulation, enabling our Veloce customers to meet their complex verification goals.”
The Veloce emulation platform is a core technology in the Mentor® Enterprise Verification Platform (EVP) – a platform that boosts productivity in ASIC and SoC functional verification by combining advanced verification technologies in a comprehensive platform. The Veloce emulation platform’s success is a result of several factors: high design capacity, speed of execution, and exceptional functionality. Now considered among the most versatile and powerful of verification tools, project teams use emulation for hardware debugging, hardware/software co-verification or integration, system-level prototyping, low-power verification and power estimation, and performance characterization.
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