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Successful ASIC/SoC Design Requires Careful IP Selection

By Vamshi Krishna – Senior IP Field Application Engineer, Open-Silicon

Today’s dynamics in the semiconductor industry demand highly precise products with short design cycle times, low manufacturing costs and careful timing for market entry. All of these elements play a key role in the success of ASICs and SoCs. To meet these demands, ASIC/SoC companies, in most cases, are compelled to leverage an open-market IP rather than develop an IP in house. This article gives insight into the aspects that ASIC companies have to consider while making reliable IP selections for ASICs/SoCs from the open-market.

A comprehensive understanding of the technical aspects related to design, cost and schedule of the product is a must to make a right selection of IPs for the ASIC. For example, a high precision product delivered without adhering to schedule, cost or to commercial implications in the market will be of no success. One must carefully consider all of these elements when designing and delivering an ASIC/SoC.

IP – Design Considerations:

In addition to understanding the “logical” requirements for building an ASIC, one must also carefully consider the “non-logical”, but still technical, aspects in the selection of an IP to ensure the design completely complies with the required specifications. A few of these are:

Power and Performance: An ASIC designer must have a clear understanding of the end application and its power and performance requirements in order to consider the right IP for the design. Determining the right sweet spot on the power-performance graph, prior to deciding on the IP, is critical to ensure optimal power and performance of the product. For example, a power hungry IP for a mobile device application does not yield desired results. On the other hand, an IP with low power consumption and  lower performance will turn out to be a bottle neck if the application demands high performance (like servers or datacenters).

Area and Orientation: In most cases, selecting a right process node helps in arriving at a design with optimal form factor, power and performance requirements for an ASIC. However, the area of an ASIC can be further optimized by ensuring proper due-diligence in comparing IP area numbers and their available orientations from multiple sources (IP vendors). The orientation of the IP determines its placement in an ASIC. Therefore, choosing an IP with the best orientation can optimize the area of the ASIC. Process selection often helps in determining design trade-offs in power, performance and cost.

IP – Cost Considerations:

The cost of an ASIC depends not only on the process node and die area parameters, but also on design NRE, die manufacturing and packaging. The right selection of IPs can reduce these costs too. Following are few factors that determine the overall development cost of a product:

Design NRE: Even though it’s a one-time cost, design NRE contributes to the product development cost significantly. A robust design approach with the right IPs is necessary to avoid any re-design (re-spin) of the product. To ensure this robust design, it is recommended, wherever viable, to select and use silicon-proven IPs for the product design. There is always some design and schedule risk associated with non-silicon proven IPs.

Manufacturing NRE: Die manufacturing cost mainly comprises of wafer cost and mask costs; the latter being a major component. Mask costs can be lowered by implementing a design with the lowest possible number of metal stacks and by making use of the minimum number of unique devices (Vt) needed in the design (which in turn is related to metal count). One must select an IP with minimal unique devices and the lowest metal stack, while ensuring the design is 100% functional, to reduce die manufacturing cost.

Package NRE: Flipchip packaging cost is more expensive compared to that of wire bond packaging. Choosing the right IP is key in reducing package NRE. In general, any high speed IP (> 6Gbps speed) will be designed and proven in a flipchip package. However, thorough market research may provide an option of wire bond IP, which is also silicon proven and can drastically reduce package NRE.

For Example, Open-Silicon works with its partners who have high-speed SerDes IPs proven in wire bond packaging. Following is a sample eye diagram of a SerDes IP, from Open-Silicon’s IP partner, running at 7Gbps with a good eye margins.

Eye diagram of a SerDes IP running at 7Gbps with a comfortable eye margin.

Eye diagram of a SerDes IP running at 7Gbps with a comfortable eye margin.

Some of Open-Silicon’s IP partners claim a silicon-proven 10G SerDes running in a wire bond package!

IP – Schedule Considerations:

Project scheduling is critical in maintaining a product’s time to market. In the ASIC industry, project scheduling depends on multiple factors, and each factor must to be carefully evaluated before starting the project. Factors that can affect project schedule, from the IP perspective, are an IP vendor’s reputation, IP maturity, and foundry capacity, just to name a few.

IP Vendor and IP Maturity: It is recommended to select the IP vendor based on the reputation they have in the industry. They should be known for providing robust IPs, having a strong support infrastructure in place to support customers, and the ability to mitigate schedule or design risk (if any). Also, wherever viable, it is recommended to use highly-mature silicon-proven IP to avoid any last minute surprises and schedule risks.

Foundry Process and Wafer Capacity: Although process node and its maturity has a say on the product reliability and cost, it is the foundry capacity and yield in production that plays a major role in a product’s TTM and volume demand. A product well designed per market needs, but fails to meet the volume demand due to low wafer capacity or yield of foundry, will not produce desired financial results.

Because the success of an ASIC/SoC weighs so heavily on IP selection, vendors are looking to design service companies to help them make informed IP decisions that ensure quality, performance and cost. A good design partner is one that has already achieved technical pre-qualification from a wide variety of IP vendors, tackled the lengthy procurement process, finalized the legal and business negotiations, and has a proven track record of successful IP integration resulting in first-time silicon success.

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