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Three Engineers and Three Months to an IoT End-Point SoC Platform

Using IP building blocks to develop a low-cost IoT end-point platform and prototype test chip in record time.

Hundreds of millions, if not billions of sensors with tiny integrated processors reside on the periphery of the Internet of Things (IoT). These end-point devices collect data from the local environment. The data reaches the Cloud over low-power wireless or wired networks for further processing and analysis. Next, computers or mobile terminals access the results to inform decision-making or to initiate actions.

End-point devices are characterized by low cost, sometimes less than $1 each, and extremely low energy consumption. Many will be in remote locations and will harvest energy from the environment or be powered by tiny coin-cell batteries. The sensors may need to operate for months or even years from these modest power sources, not least because if batteries need to be changed more frequently, the commercial viability of some applications will be called into question.

Many end-point devices communicate small packets of data infrequently. They run in sleep mode most of the time. However, that doesn’t diminish the need for robust security from the end-point, throughout the network and within the cloud.  In addition, application software must make it easy to access, control, update and maintain the devices, and systems must be scalable. Some networks that initially deploy just a few end-point nodes may grow to encompass thousands.

Challenge—Three Engineers and Three Months

System-on-chip integrated circuits (SoCs) are most frequently used in high volume applications where their high levels of functional integration simplify product design and reduce the number of components required, keeping size and costs to a minimum. Adopting SoCs also results in robust, reliable designs with fewer connections between components and often with the lowest possible energy consumption, too.

Consumer electronic devices including smartphones and tablets, where high-performance processing is a priority, use SoCs extensively. In a typical end-point sensor environment processing demands are much less stringent, and low energy consumption is often the primary consideration.

In 2015 ARM® set out to determine if, using ARM IP blocks and some of their own, a design group of just three engineers could create an IoT end-point platform and test chip within three months. The platform had to be flexible enough to facilitate rapid development of a variety of differentiated IoT solutions. Another goal of the project, dubbed ”Beetle,“ was for ARM to better understand the design challenges inherent in implementing IP for IoT devices. For example, it turned out to be the first time the design team had ever integrated Bluetooth radio IP together with embedded Flash.

The ARM Artisan® physical IP platform, tailored for IoT applications, was used to build the test chip, the design of which was compliant with ARM’s mbed™ IoT platform, in order to facilitate rapid development and prototyping. The single-chip device that resulted from the project integrates ARM IP and includes an IoT subsystem with Cortex-M processor, embedded Flash memory and a Bluetooth Low-Energy (BLE) radio.

The test chip taped out successfully in the third quarter of 2015 and demonstrated how ARM’s IoT platform minimizes risks and accelerates time-to-market. It also reduces costs by requiring minimal engineering resources.

The Beetle Platform Elements

Figure 1 shows the Beetle project’s demonstrator platform. Running mbed OS software, the test chip was fabricated in TSMC’s 55nm process technology. The test chip’s central element, the IoT subsystem, was completed in the middle of 2015. This works with Cortex®-M3 or Cortex-M4 processors, the latter being a useful option for more demanding applications where DSP functionality is desirable or necessary.

The Bluetooth Core Specification Version 4.2 is implemented in the ARM Cordio® BLE radio. This is a hard macro block. It’s designed to work efficiently with Cortex-M processors.  Engineers familiar with digital design flows can implement it quickly and easily.

The radio has a sub-1V low-power core, consuming less than 6.5mW at 1V in active mode and only 700nW in sleep mode. ARM Artisan standard cell, SRAM and general-purpose I/O physical IP libraries complement the radio and IoT subsystem.

Figure 1:  The Beetle test chip IoT demonstrator platform.

Figure 1: The Beetle test chip IoT demonstrator platform.

The mbed IoT Device Platform is the primary source of device, communication and lifecycle security. Its open-source mbed OS and the Device Connector Service handle communication with IoT end-point devices. mbed enjoys the support of more than 50 mbed ecosystem partners and 175,000 developers. As a result, engineers can take full advantage of hundreds of compatible components, cloud services and software tools. mbed OS uVisor uses its Memory Protection Unit (MPU) to create isolated security domains on the Cortex-M processor and the mbed Transport Layer Security (TLS) manages communication security. Where required, security may be further enhanced using hardware features such ARM’s True Random Number Generator (TRNG), which is implemented in the Beetle.

Rapid Integration

Even digital designers with little experience of working with radios or embedded Flash can implement the Beetle platform quickly and effectively using standard digital design flows and tools. To assist engineers whose experience is primarily in the digital domain, layout guidelines are provided.

The physical design kit (PDK) includes timing and physical abstract models and is EDA-tool agnostic. Engineers do not need a lot of RF or mixed-signal experience because they are able to treat the BLE radio just like a digital IP block using a macro-like methodology. The host controller interface is completely digital, and an AMBA-AHB bus provides the Cortex-M IoT subsystem interface.

Asynchronous operation eliminates any dependency on clock timing between the host control and radio; sideband signals are used for radio power and clock control. An integrated pad ring protects sensitive radio I/O. Following design best practice, including guardbanding between the radio and logic circuits and ensuring effective power supply decoupling, minimizes the risk of noise issues. Macro blocks of metal-oxide-metal (MOM) capacitors create a tiny bulk decoupling capacitor for the power supplies. The radio design needs just 12 external components: an antenna, two inductors, two crystals and seven capacitors.

Integrating embedded Flash IP (from TSMC) was challenging because the memory needs 1.2V/2.5V supplies for read/write. Shifting to 2.5V is achieved using the ARM Artisan physical IP platform, which features regular and thick-oxide versions of level shifters. An embedded Flash cache is used to keep memory accesses to a minimum because these are significant contributors to power consumption, even in power-optimized systems.

The Beetle test chip has two banks of 128K for application flexibility. For example, over-the-air code updates may be implemented in one and application code in the other. The cache and Flash controller are part of the IoT subsystem, which will support up to 512K of Flash for more complex nodes.

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Looking Ahead

The Beetle platform and ARM Cortex-M Prototyping System (MPS2) development board are available now. ARM continues to enrich its IoT development ecosystem to help engineers reduce the development time for IoT end-point devices. The company is proposing further security enhancements with the TrustZone® CryptoCell IP, and Artisan libraries for more advanced process nodes could lead to even better energy efficiency in the future.

The Beetle project has demonstrated that it’s possible to build a differentiated, very-low-power and cost-constrained, IoT end-point device SoC in a short time with a small engineering team. Given the pace at which the IoT is growing, this creates valuable opportunities for any company wishing to capitalize on the opportunities it presents.


WhitfieldTim Whitfield is Director of Engineering for ARM’s Hinschu Design Center in Taiwan. He joined ARM in 2000 and was involved with the first ARM synthesizable core, and a founder member of the physical implementation group. Tim technically led a number of CPU macro hardening projects for ARM partners and foundry projects. He has also led a number of key ARM development and test chips used for SW development and IP validation. These developments have spanned multiple process nodes from 180nm to 16nm. Tim moved here three years ago to create a design center focused on ARM implementation at advanced process nodes. The design center is now expanding to include customer support services and the recently announced ARM M-class CPU design team. Tim Whitfield graduated from Brunel University, UK in 1995 with a degree in Electrical and Electronic Engineering. Prior to join ARM, he worked for GEC and Fujitsu Telecommunications.

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