How to Boost Verification Productivity with SystemVerilog/UVM and Emulation
Use of emulation for hardware-assisted testbench acceleration is growing as design verification teams find that simulation alone cannot deliver the coverage or performance needed to get large, complex designs to market on time. If your design requires millions of clock cycles to fully verify, you need both simulation and emulation.
Let’s first describe what we mean by testbench acceleration. Testbench acceleration involves an RTL design running in a hardware emulator and interacting with a testbench running on a workstation via emulation-ready, accelerated transactors. This makes emulation easier to use and boosts verification performance. You get both the modeling flexibility and functionality of simulation at the IP and block levels and the enormous performance gains of emulation at the chip, sub-system, and system levels — including the ability to verify embedded software and hardware at the same time.
The goal, then, is to deploy a single, unified testbench environment that is flexible, fast, and portable, moving with you from the block to system level, from simulation to emulation. The principal benefits of a unified testbench environment are increased verification performance and productivity, vertical reuse through platform portability, reduced development effort, and substantially lower design tape-out risk.
So how can you reap these benefits? It is actually more straightforward than you might think to create a unified testbench flow for both simulation and emulation. We’ve distilled it down to three steps:
- Employ two separated domains, an untimed HVL domain and a synthesizable HDL domain.
- Model all timed testbench code for emulator synthesis in the HDL domain, leaving the HVL domain untimed.
- Devise a transaction-level, function-call based communication API between HVL and HDL domains.
While not intrinsically difficult, it will be more intuitive with less effort if you factor in emulation from the get-go when developing your testbench. If done right, using emulation-ready, accelerated transactors shifts testbench load to the emulator, with significant performance benefits. At the same time, you don’t sacrifice simulator verification capabilities and integrations, such as modern coverage-driven and assertion-based techniques and tools.
Imagine running a test that takes hours (or days) in a simulator in mere minutes with the added boost of an emulator. Imagine the number of design and testbench iterations that can be explored with these time savings. Imagine how much extra verification can be accomplished to further mitigate design risk.
We describe the details of SystemVerilog and UVM testbench acceleration using hardware emulation, what we call a dual-domain framework for transaction-based testbench acceleration, in a series of three papers. The papers introduce the fundamental concepts and present the architectural and modeling requirements for SystemVerilog and UVM testbench acceleration using hardware emulation, and the steps to achieve optimal acceleration speed-up.