Aldec Extends Spectrum of Verification Tools for Use in Digital ASIC Designs
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware- assisted verification solutions for digital system designs, announced that its verification tools suite, used for over 30 years of complex FPGA design verification, is available for ASIC chip design.
Covering the full digital verification flow from design and test planning through simulation, emulation, and prototyping, Aldec’s popular verification tools help designers in small and large fabless companies ensure that complex digital ASIC designs meet all functional and timing requirements before being committed to a mask set, helping to protect against the high cost of a mask respin.
Aldec’s verification suite includes cost-effective, high-performance tools for HDL verification across the full range of industries, including computing, storage, communications, and the Internet of Things, as well as safety-critical applications within aerospace, medical, automotive, and industrial systems.
“Engineers need a reliable verification partner that suits their budgets while still providing a high level of support,” said Dr. Stanley Hyduke, Aldec Founder and CEO. “To fill this need, we at Aldec have extended our spectrum of verification tools for use in digital ASIC designs.”
Aldec tools support all phases of the digital flow, from design planning through to prototyping for software verification.
- Spec-T RACER™ manages requirements/specifications, providing capture, mapping to tests, and full traceability for compliance with critical-systems standards like ISO-26262 for automotive, IEC-61508 for industrial and DO-254 for avionics.
- ALINT-PRO™ provides VHDL and Verilog code analysis (linting) as well as clock-domain-crossing (CDC) verification. Aldec’s libraries contain well-established criteria for basic coding, CDC, DO- 254, STARC, and RMM standards.
- Aldec’s high-performance Riviera-PRO™ simulator speeds verification through both fast incremental compilation and fast multi-core simulation execution. It accepts code written in VHDL, Verilog, SystemVerilog, SystemC, and mixtures of these languages. It supports the latest verification libraries, such as OVM/UVM, along with many specialized graphical UVM debugging tools. It offers code and functional coverage capabilities with coverage analysis tools to support a metric-driven verification approach. It can handle the multi-million-gate designs typical of ASIC projects.
- The HES-7™ board and HES-DVM™ software combine to provide a hardware emulator with a SCE-MI 2 interface. HES-DVM manages design setup, design compiler integration, and debug instrumentation. It partitions large designs across multiple HES-7 boards and supports several host communication schemes for different emulation modes:
- PLI/VHPI for bit-level acceleration
- SCE-MI 2 and DPI-C for function-based transaction-level and UVM verification
- SCE-MI 2 and TLM for macro-based hybrid emulation with a virtual platform running processor models or a SystemC testbench
- In-circuit emulation with speed adapters for external data streams and interfaces Aldec hardware debugging provides 100% visibility into the design at the RTL level.
- The CT S™ platform enables at-speed module execution for catching bugs that are evident only at high speeds.
- The HES-7™ boards give software programmers a hardware prototype for high-speed testing of software against the hardware design.
- The verification tools are supported by a broad set of verification IP (VIP) libraries that save time and effort while ensuring thorough design checkout.