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Overcoming the Traditional Bottlenecks in Transistor-level and Cell-level Custom Design Flows

Typically, there are three phases in custom design flows where time to final layout has been a bottleneck: area estimation, layout / simulation cycle and final layout. Pulsic, a provider of physical design tools for precision design automation, will demonstrate solutions to overcome those bottlenecks at DAC 2016: Pulsic Animate™ and Pulsic Unity™ Chip Planner.

Pulsic Animate surpasses traditional approaches to automating transistor-level IC design, which have attempted to improve on portions of the design flow, but have not managed to generate near “manual-quality” layout without significant user intervention. Animate is the first complete automated layout system built from the ground up for transistor-level analog and custom-digital design. Animate overcomes layout bottlenecks by delivering an easy-to-use flow that reads in a schematic, automatically extracts design constraints, and employs patent-pending, multi-threaded PolyMorphic™ technologies to very quickly produce abstracted “Blueprint” representations of the designs. Many different “Blueprints” are generated in minutes or seconds. These layout “Blueprints” are guaranteed to contain no opens or shorts and can therefore be extracted to produce accurate parasitics that can be fed back into simulation. Animate’s constraint recognition capability automatically generates constraints based on netlist topology analysis, eliminating the need for manual constraint entry and management.

Layout “Blueprints” can be saved to an OpenAccess database and modified by the user to produce high-quality, fully placed and routed, detailed layouts in a fraction of the time taken using a traditional approach.

For more detailed information on Pulsic’s automated analog layout solution, see  http://www.pulsic.com/Animate/ For an exclusion demonstration of Pulsic’s Animate while at DAC, click here.

“For too long now, manual layout has persisted in analog design because previous efforts at automation could not approach the level of quality offered by manual designers,” said Mark Williams, co-founder and CEO, Pulsic. “Animate provides value in multiple areas across the design flow. Since the introduction of Animate last year, we have been receiving accolades from both circuit designers and layout engineers who are able to do accurate simulations early in the design process and to get to faster layout closure with high quality of results.”

Pulsic Unity Chip Planner is the first and only hierarchical, top-down and bottom-up floorplanner built for cell-level custom design. Although automated floorplanners are a part of standard digital design flows, they do not address all the needs of custom designers. Custom designers face unique challenges, such as large hard-IP blocks, analog content, and few metal layers available for routing. At leading-edge nodes (28 nm and below), process rules constrain designs in new ways, and the extreme aspect ratios of the routed wires and highly resistive metals make understanding parasitics critical.

Unity Chip Planner enables custom design teams to manage growing complexity while accelerating design closure and improving design quality. By providing a high level of automation, Unity Chip Planner gives accurate results quickly and enables custom design teams to respond to netlist changes quickly and easily. In addition, Unity Chip Planner can produce early estimated parasitic extraction data from an unrouted — or partially routed — floorplan, allowing multiple architectures to be explored and validated without time-consuming detailed implementation of the layout.

Unity Chip Planner provides all the necessary tools and technologies within a fully integrated floorplanning environment. The guided flow offered in Unity Chip Planner helps ensure faster design closure with successful results every time. For more detailed information, please visit:  http://www.pulsic.com/products/pulsic-planning-solution/unity-chip-planner/ For an exclusion demonstration of Pulsic’s Unity Chip Planner while at DAC, click here.

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