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Closed-Loop DFM Solution Accelerates Yield Ramps

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Mentor Graphics Corp. announced that Samsung Foundry’s closed-Loop design-for-manufacturing (DFM) solution uses production Mentor Calibre and Tessent platforms to accelerate customer yield ramps.

In the Closed-Loop DFM flows, Samsung integrates its DFM kits with its testing and manufacturing expertise to identify integrated circuit design patterns that are most likely to impact manufacturing yield, thereby helping customers improve design quality, yield, and ramp to production.

“We can detect the risks in customer products and prevent them,” said K.K. (Kuang-Kuo) Lin, Director, Foundry Marketing Ecosystem, Samsung Semiconductor. “We have seen yield gain of up to 8.5%. In terms of the post-manufacturing yield analysis, we have seen the benefits of around 2%. These numbers are not guaranteed because each product is different, but from our experience, these are the numbers we have seen.”

The Samsung solution extracts customer yield-averse design patterns, feeds that information forward to optimize manufacturing and testing, and closes the loop with feedback from silicon results for product design and yield improvement. This solution is not only useful to initial customer designs, but it also allows learning from current production designs to be applied to next-generation designs from that same customer across entire product families.

As shown in Figure 1, Samsung’s foundry offerings cover the needs of devices, ranging from the IoT to consumer, mobile computing, high end computing to automotive. The company, which first got into the foundry business in 2005, claims to be the first foundry to have high-k metal gates in production (in 2011), the first foundry to offer FinFET risk production (in 2013) and the first foundry to tape out a 10nm product. “We are also at the forefront of 7nm. We call it 7LPP, which will be based on EUV,” he added.

Figure 1

With the end goal of rapid yield ramp for new production introduction, Samsung turned to Mentor Graphics tools for pre-production DFM, which it calls PRISM (pattern recognition and identity scoring methods), which runs on Mentor’s Calibre platform. For this pre-production phase, “we provide very comprehensive process-aware DFM sign-off kits and optimization flow for the designers so they can double-check and verify, prevent any DFM issues during the design phase,” Lin said.

The other component of closed-loop DFM is in post-manufacturing. Samsung has developed as set of tools called FLARE (Failure analysis And yield Rank Estimation with DFM hotspot database), which runs on Mentor’s Tesset platform.

Figure 2 shows how PRISM and FLARE work together in a closed-loop fashion for pre- and post-production DFM.

Figure 2

“Every design has its idiosyncrasies and its unique signatures because layout designers can be pretty creative,” Lin explained. “We use PRISM to do extensive pattern analysis and then do optimization during the data prep and also use the pattern analysis result to drive in-line inspection.”

Once the wafer is manufactured in the fab, FLARE involves mapping a yield learning database with EDS, (electrical engineering die-sort data). “We’ll combine them to do yield pareto data analysis and also mapping analysis. From those deep learning, we are able to prioritize which part of the fab process we can improve. We can also feedback to the DFM kit which we use in the design phase, which gives the designer feedback on what they can further improve,” Lin said.

At the heard of PRISM is a defect database built from test vehicles and existing products (Figure 3). “We put all the patterns that we know into this defect database,” Lin explained. “We also couple it with some very novel things. We use a layout schematic generator from Mentor to increase the coverage, to enumerate all the possible patterns. And then we also have meta data and simulators to do yield prediction of those known defects from different sources.”

Figure 3

“Once a customer product comes into Samsung foundry, we will check against the known defect database. Then we will do prediction in terms of the process margin and feed-forward this data into the subsequent steps of data prep or retargeting, and in-line inspection so we can prioritize our resources to know what to inspect and what not to in the manufacturing steps,” Lin said (see Figure 4).

Figure 4

“FLARE accelerates the learning in the fab to bring up customer products in our foundry. It helps the customer achieve their time to market. It also saves on fab operation costs, so it’s a win-win situation for everyone,” Lin said.

The Closed-Loop DFM flows are in production use today for customers of Samsung Foundry services. While proven in 14 nm technology, the flows can be used for ICs manufactured with other Samsung process nodes.

At the 2016 Design Automation Conference, Mentor and Samsung are co-hosting a lunch seminar entitled “Accelerate Yield Ramps with Samsung Foundry Closed-Loop DFM and Mentor Tools.” The event is Monday, June 6, from 12:00 to 1:30 PM. Interested customers can register for the event using this registration link.

https://www.mentor.com/products/ic_nanometer_design/events/samsung-dac-lunch-seminar

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