Ausdia Introduces Timevision ModeMerge
New system-on-chip (SoC) designs continue to see an increase in the number of timing modes used to verify the behavior of the SoC in signoff. The number of modes has been expanding even more rapidly with the proliferation of multiple test modes, such as low- and high-speed capture, serial or parallel scan, built-in self-test (BIST), memory test, etc. Engineers who write the Synopsys Design Constraint (SDC) files for these blocks try to manually optimize their SDC files to reduce the absolute number of design modes by manual analysis and by making tradeoffs that hurt optimization and accuracy. In addition, designs are starting to see more “mode conflicts,” where optimizing one mode impacts optimization in other modes, leading to non- convergent behavior in timing closure.
Ausdia, the leading developer of timing constraints verification and management solutions that complement timing signoff for complex SoC designs, tackles this problem head-on with a new option to its comprehensive Timevision solution. At DAC, Ausdia introduced Timevision ModeMerge, which takes multiple functional and test timing modes, represented as SDC files, and merges them into a single SDC timing mode. This allows the timing behavior of multiple distinct modes to be represented as a single timing mode with a single SDC, enabling place-and- route tools and static timing tools to accurately optimize and verify the design in a single session.
Timevision is a comprehensive timing constraints development, verification and management solution that complements all implementation and timing signoff flows, with the capacity to handle over one billion cells and thousands of clocks. Introduced at DAC 2012, Timevision integrates with all aspects of the design flow and is used before synthesis, before DFT insertion, before place and route, and when signoff timing is being run. Timevision helps designers create good SDC constraints and is a verification platform for existing timing constraints.
ModeMerge uses innovative new technology to ensure accurate SDC merging across all possible SDC clock topologies, as well as accurate backtracking so that the source of all merged SDC data can be easily determined. The latest in SDC timing constructs are used to efficiently manage the timing behavior of the resulting mode, ensuring a very limited runtime impact of the merged mode in the timing analysis tools. This allows SoC teams to optimize their place-and-route and static timing usage as well as to reduce the load on engineering teams for timing closure activities to a simpler, more straightforward signoff process. For instance, the runtime to merge a 3.3M instance design with 7 modes and 25 clocks per mode is less than 50 minutes and 21G of memory (including time to load each timing mode).
Advantages of the ModeMerge capability include:
- Merges all clock topologies without restriction, so there is no need to rewrite SDC files to take advantage of merging.
- Compresses all functional and timing test modes and is not just limited to two modes.
- Does not require any manual inputs or directives, so there is no need for engineers to understand or provide guidance on key design points or decisions in order to generate merged mode.
- Works directly from SDC source files; no separate files or manual effort is needed to generate mode merged data.
- Compresses the resulting SDC for readability and performance,
“We kept hearing from customers that other mode merge products were not able to merge all designs, or that they had a lot of restrictions on the types of SDC topologies that would be supported across modes. In addition, the runtimes of these tools often ran into one or two days, obliterating any advantage of using a mode merged SDC file,” said Ausdia president and CEO, Sam Appleton. “Most design teams, and many SoC timing verification teams, have been trying to get all behavior represented inside a single session timing mode for faster closure and analysis without compromising accuracy. Now, we’re offering an advanced solution for optimizing place-and-route and timing closure on designs with more than one timing mode.”