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Time to Uncover the Process Mystery for Competitive IC Designs

There have been no available EDA tools dedicated to helping designers understand process and facilitate process development interactions.

The semiconductor industry is moving forward with new and innovative chip designs. Who couldn’t be impressed with the newest Apple products, newly emerging IoT applications and the way in which large companies are moving into datacenter storage? With these bold moves, come big challenges for project teams.

Semiconductor processes have long been a mystery for many circuit designers. They didn’t need to worry about how chips were fabricated most of the time, thanks to the many EDA innovations that make their jobs easier and complex designs possible.

The success of the foundry-fabless business model over the past 20 years has been one of the main drivers of the booming of semiconductor industry. The cooperation between foundries and IC designs in fabless companies for process development worked so well that process engineers and circuit designers only needed to focus on their area of expertise. EDA flows simplified the interaction by using process design kits (PDKs) as the information carrier for circuit designs and sent tapeout databases (GDSII) back to the foundry for chip fabrication. Most designers didn’t need to dig into the process.

That was then. The designer now is forced to understand process and devices when moving to smaller nodes in order to achieve more competitive designs. Because process is the least understood, the loose link between process and design should be enhanced to improve design and tapeout confidence.

Knowing processes and devices would help designers make better use of the process platform and improve designs. Device geometries are getting smaller and new structures such as FinFET and FD-SOI are becoming mainstream leading to complicated device characteristics and SPICE models, the most critical components in the PDK. They represent a process platform’s performance and device characteristics, fundamental to good circuit design. A solid understanding of SPICE models becomes necessary to make full use of the process. This is true not only for designs at advanced nodes at 28nm beyond, such as 16nm, 14nm and10nm, but critical for some refreshed older technologies for IoT/Wearable applications.

Running a full evaluation of process and device performance would provide guidance to better select device types, optimize device sizes and bias conditions, trade-off circuit speed and power. The same logic can be applied to generic circuit designs at any technology node, such as analog designs at 180nm or above.

This practice is used mostly within IDMs where process and design teams have fairly direct channels to work cooperatively. Recently, fabless companies strengthened links with foundries to understand the process and devices to improve design output or for process-circuit co-design for high-end chip designs with more aggressive speed, power and performance specifications.
These efforts are significant. Most companies don’t have the resources and time to build a dedicated team and flow and there have been no available EDA tools dedicated to helping designers understand process and facilitate process development interactions. Increasing time-to-market pressures and tough competition drive the need to a higher priority.

Without an EDA tool, current practices can easily take weeks or months to build, maintain and run a flow by creating scripts or SPICE netlists for different evaluation items. It’s practically impossible to run through the cases to generate a full picture of process platform for designers within a short turnaround time.

As a result, it’s hard to come up with a set standard for process evaluation before using it in design, as efforts can vary for different projects. For a big corporation with many design projects, dealing with multiple foundries, using multiple technology nodes and different process platforms, this type of work is critical to its success however becomes overloaded.

Figure 1. A tool for circuit designers to explore, compare and verify PDK libraries would help them better manage process platforms and assist design development.

Figure 1. A tool for circuit designers to explore, compare and verify PDK libraries would help them better manage process platforms and assist design development.

Furthermore, the complexity of SPICE models is exploding (Figure 1). Thousands of parameters in each model and a huge model library file with more than 100K lines of code are quite common. Macro models with complicated layout-dependent effects and random variations add more dimensions of complexity.

Complexity and time pressures are huge. An EDA tool to manage both would be indispensable.

One tool could use the PDK library as the input to explore, compare and verify models. It could help designers understand and explore the process-design space to guide process platform selection and enable quick adoption of the process and assist designs. It would help designers dig into the process from different angles, including a high-level summary of the process and device performance, device characteristics, statistical behavior and circuit performance related to the application. This should enable designers quickly adopt and make full use of a process platform that suits their needs.

Designers could systematically evaluate a process or benchmark different process platforms by using any device or circuit-level evaluation target and criteria, improving their understanding of devices and processes and providing further guidance to improve circuit designs. A tool like this could help designers easily find out changes in device or circuit performance of new process revisions.

Evaluation results such as new target specifications could be fed back to the process development team for retargeting. In the past, CAD, design and process teams worked separately using different languages or disciplines. With a tool like this, process development and circuit design teams would use it as a common platform to interact for more efficient process-circuit designs.
An EDA tool could improve work efficiency for faster turnaround and offer a much more complete picture of the process for more competitive designs. It would bridge the gap between foundries and fabless designs.
_________________________________________________________________________________________________________________
DrDr. Zhihong Liu currently serves as the Chief Executive Officer and the Chairman of the Board of ProPlus Design Solutions, Inc. Most recently, he was corporate vice president for CSV R&D at Cadence Design Systems Inc. Dr. Liu co-founded BTA Technology Inc. in 1993 and invented BSIMPro, the leading Spice modeling product. He also served as the president and CEO of BTA Technology Inc. and later Celestry Design Technology Inc., acquired by Cadence in 2003. Dr. Liu holds a Ph.D. degree in Electrical Engineering from the University of Hong Kong and co-developed the industry’s first standard model (BSIM3) for IC designs as one of the main contributors at the University of California at Berkeley.


The semiconductor industry is moving forward with new and innovative chip designs. Who couldn’t be impressed with the newest Apple products, newly emerging IoT applications and the way in which large companies are moving into datacenter storage? With these bold moves, come big challenges for project teams.
Semiconductor processes have long been a mystery for many circuit designers. They didn’t need to worry about how chips were fabricated most of the time, thanks to the many EDA innovations that make their jobs easier and complex designs possible.
The success of the foundry-fabless business model over the past 20 years has been one of the main drivers of the booming of semiconductor industry. The cooperation between foundries and IC designs in fabless companies for process development worked so well that process engineers and circuit designers only needed to focus on their area of expertise. EDA flows simplified the interaction by using process design kits (PDKs) as the information carrier for circuit designs and sent tapeout databases (GDSII) back to the foundry for chip fabrication. Most designers didn’t need to dig into the process.
That was then. The designer now is forced to understand process and devices when moving to smaller nodes in order to achieve more competitive designs. Because process is the least understood, the loose link between process and design should be enhanced to improve design and tapeout confidence.
Knowing processes and devices would help designers make better use of the process platform and improve designs. Device geometries are getting smaller and new structures such as FinFET and FD-SOI are becoming mainstream leading to complicated device characteristics and SPICE models, the most critical components in the PDK. They represent a process platform’s performance and device characteristics, fundamental to good circuit design. A solid understanding of SPICE models becomes necessary to make full use of the process. This is true not only for designs at advanced nodes at 28nm beyond, such as 16nm, 14nm and10nm, but critical for some refreshed older technologies for IoT/Wearable applications.
Running a full evaluation of process and device performance would provide guidance to better select device types, optimize device sizes and bias conditions, trade-off circuit speed and power. The same logic can be applied to generic circuit designs at any technology node, such as analog designs at 180nm or above.
This practice is used mostly within IDMs where process and design teams have fairly direct channels to work cooperatively. Recently, fabless companies strengthened links with foundries to understand the process and devices to improve design output or for process-circuit co-design for high-end chip designs with more aggressive speed, power and performance specifications.
These efforts are significant. Most companies don’t have the resources and time to build a dedicated team and flow and there have been no available EDA tools dedicated to helping designers understand process and facilitate process development interactions. Increasing time-to-market pressures and tough competition drive the need to a higher priority.
Without an EDA tool, current practices can easily take weeks or months to build, maintain and run a flow by creating scripts or SPICE netlists for different evaluation items. It’s practically impossible to run through the cases to generate a full picture of process platform for designers within a short turnaround time.
As a result, it’s hard to come up with a set standard for process evaluation before using it in design, as efforts can vary for different projects. For a big corporation with many design projects, dealing with multiple foundries, using multiple technology nodes and different process platforms, this type of work is critical to its success however becomes overloaded.
Furthermore, the complexity of SPICE models is exploding (Figure 1). Thousands of parameters in each model and a huge model library file with more than 100K lines of code are quite common. Macro models with complicated layout-dependent effects and random variations add more dimensions of complexity.
Complexity and time pressures are huge. An EDA tool to manage both would be indispensable.
One tool could use the PDK library as the input to explore, compare and verify models. It could help designers understand and explore the process-design space to guide process platform selection and enable quick adoption of the process and assist designs. It would help designers dig into the process from different angles, including a high-level summary of the process and device performance, device characteristics, statistical behavior and circuit performance related to the application. This should enable designers quickly adopt and make full use of a process platform that suits their needs.
Designers could systematically evaluate a process or benchmark different process platforms by using any device or circuit-level evaluation target and criteria, improving their understanding of devices and processes and providing further guidance to improve circuit designs. A tool like this could help designers easily find out changes in device or circuit performance of new process revisions.
Evaluation results such as new target specifications could be fed back to the process development team for retargeting. In the past, CAD, design and process teams worked separately using different languages or disciplines. With a tool like this, process development and circuit design teams would use it as a common platform to interact for more efficient process-circuit designs.
An EDA tool could improve work efficiency for faster turnaround and offer a much more complete picture of the process for more competitive designs. It would bridge the gap between foundries and fabless designs. ◆
Dr. Zhihong Liu currently serves as the Chief Executive Officer and the Chairman of the Board of ProPlus Design Solutions, Inc. Most recently, he was corporate vice president for CSV R&D at Cadence Design Systems Inc. Dr. Liu co-founded BTA Technology Inc. in 1993 and invented BSIMPro, the leading Spice modeling product. He also served as the president and CEO of BTA Technology Inc. and later Celestry Design Technology Inc., acquired by Cadence in 2003. Dr. Liu holds a Ph.D. degree in Electrical Engineering from the University of Hong Kong and co-developed the industry’s first standard model (BSIM3) for IC designs as one of the main contributors at the University of California at Berkeley.
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