Third DVCon India Ready for Liftoff
By Thomas L. Anderson, Vice President of Marketing, Breker Verification Systems, Inc.
Many design and verification engineers know that the premiere industry event for their professions is the Design and Verification Conference and Exhibition (DVCon). Originally a Silicon Valley show, DVCon has expanded to Europe and India, and will add China next year.
DVCon India has been very successful by any measure. The first event in 2014 drew more than 450 attendees from more than 80 different companies and universities; last year attendance grew to more than 600. For the third year, the conference will be bigger and better than ever, held September 15-16 in the familiar setting of the Leela Palace Hotel in Bangalore.
The full program is available online at https://dvcon-india.org/agenda. As usual, there are two tracks to the technical program: electronic system level (ESL) and design and verification (DV). Both include keynote talks by industry experts, deeply technical presentations and posters from hands-on engineers, in-depth tutorials, and a panel on a hot topic. This year features increased involvement from academia and participation from many leading companies with design and verification teams in India.
The keynote speakers include executives from Mentor, Synopsys, Canon, and Cadence and a professor from IIT Madras. Most of these are presented in general sessions, after which attendees may attend any of the sessions in either track, switching back and forth as they wish to hit topics of interest. There are 39 presentations and 13 posters on the program, covering a very impressive range of topics. The ESL track includes:
- ESL power and energy modeling
- System-level design techniques
- Hardware/software co-design and co-simulation
- System-on-chip (SoC) architecture evaluation
The ESL panel debates how to provide an entry-level vehicle for the Internet of Things (IoT) marketplace. The DV panel focuses on how verification flows may evolve in the future, including the roles of simulation, emulation, and formal. The presentations in the DV track cover ever more topics:
- Universal Verification Methodology (UVM) and SystemVerilog
- Assertions and formal
- Verification of low-power designs
- Processors and SoCs
- Analog/mixed-signal (AMS) verification
- Acceleration and co-simulation
Both tracks feature tutorials that provide practical instruction in some of the leading topics for today’s chip architects, designers, and verification engineers. The ESL track covers high-level synthesis, SystemC TLM2.0, emulation, virtual prototyping, and a case study of Infineon’s AURIX Microcontroller. Tutorials in the DV track address such topics as advanced UVM coding techniques, UVM reuse methodology, verification and debug for Internet of Things (IoT) devices, portable stimulus, and designing for quality.
This year’s conference continues DVCon India’s focus on the importance of industry standards and how best to leverage them. Standards addressed include IP-XACT, SystemC, Transaction-Level Modeling (TLM), SystemVerilog, UVM, and the emerging area of portable stimulus. Attendees can find out how EDA tools support these standards by visiting the vendor exhibition. Booths are open both days, with most activity occurring during lunch and tea-time breaks.
The technical nature of the conference is complemented by the many opportunities for attendees to network with their peers. In addition to the breaks between sessions, Thursday evening features dinner and entertainment. Even the closing ceremony is a must-attend session, with awards and celebrations for a successful event.
Breker is proud to be a supporter of DVCon India for the third time. We will present a joint tutorial on portable stimulus with other members of the Accellera Portable Stimulus Working Group (PSWG) and we will have a booth in the exhibition area. For more information, or to register to attend, visit http://dvcon-india.org/. We‘ll see you in Bangalore!
About Thomas L. Anderson
Thomas L. Anderson is Co-Chair of the DVCon India Promotions Committee and Secretary of the Accellera Portable Stimulus Working Group (PSWG). He serves as vice president of marketing at Breker Verification Systems, the SoC Verification Company. He has more than a dozen years of experience in EDA verification applications and marketing, having served in increasing responsible roles at Cadence, Synopsys and 0-In Design Automation. Anderson holds a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst and a Master of Science degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology (MIT).