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Quo Vadis SPI?

How I3C is replacing SPI and the benefits—including cost and energy savings—we can expect.

The MIPI I3C interface is poised to replace the venerable serial peripheral interface (SPI) in many applications, including mobile-smartphone, legacy-embedded, and more recent mobile-influenced applications. Although MIPI Alliance developed I3C as an upgrade to I2C with sensor interconnections as the primary application, the vision was its use in a broad range of other applications that have used SPI. This proposition is the focus of this article.

MIPI I3C Development

The MIPI Alliance initiated development of the MIPI I3C interface to solve the interconnect problem with sensors in a smartphone. As the number of sensors increased, and with each sensor nominally using I2C or SPI with one or more sideband signals, the number of signals to connect to the host processor became prohibitive and a solution to minimize pins was desired. MIPI I3C was developed primarily to improve sensor interconnect efficiency with a modern interface backward compatible to the decades-old two-signal I2C interface. Figure 1 illustrates the improvement achieved when the new interface is deployed as an I2C replacement and whereby shared I3C clock and data lines carry both data and sideband signals.

Figure 1: Sensor application I2C migration to MIPI I3C

Figure 1: Sensor application I2C migration to MIPI I3C

SPI and MIPI I3C Interface Basics

As shown in Figure 2, the basic SPI consists of 4 signals, annotated “SPI (4)”. Naming from the master host perspective is: DATA_OUT, DATA_IN, CLK_OUT, and CHIP_SELECT. Most hosts today support a clock speed of 30-50 MHz, yielding an approximate 20-30 Mbps throughput after application protocol accounting. Many applications and system designers often use additional out-of-band signals for functions such as interrupts (INT) and resets (RESET), hence a typical SPI can consist of 4-6 signals or more. Also note that SPI can be used in a multi-point configuration from the one master to multiple slaves, with slave data flow identified by the active CHIP_SELECT line, but for simplicity here we focus only on point-to-point implementations.

The MIPI I3C interface supports data throughput speeds up to 33 Mbps across its 2-signal data/clock interface, annotated “I3C (2)”, and it supports advanced features that enable the elimination of sideband signals via two features: In Band Interrupt (IBI) and virtual GPIO (VGI). The IBI feature enables a slave to notify a master via an in-band mechanism and hence can eliminate discrete signals such as interrupts (INT). The VGI feature captures physical GPIOs in dedicated hardware and formats them for transmission as a special I3C message, identified at the receiver by hardware that reproduces the physical GPIO. VGI can often absorb more hardware-centric signal functionality, such as RESETs.

The 4-6 signal SPI can thus be reduced to a 2-signal I3C interface plus RESET, as shown in Figure 2, where the INT line is absorbed into an IBI message but the physical out-of-band RESET signal is maintained in physical form. In some implementations, the RESET function can be absorbed by IBI, and in other cases via VGI. And, I3C sustains about the same data throughput as the SPI it may replace, each achieving about 30 Mbps. As shown in Figure 1, I3C clearly supports multi-point configurations, although Figure 2 illustrates the simplest point-to-point configuration, which may be a common implementation where the highest data throughput between two entities (like master and peripheral slave) is desired.

Figure 2: Basic SPI and MIPI I3C Configurations

Figure 2: Basic SPI and MIPI I3C Configurations

SPI Applications

The following describes a set of application peripherals that have traditionally used one or more SPIs and sidebands. These include A. camera, B. touch, C. audio codec, and D. Near Field Communication (NFC); other applications are also identified.

A. Camera control interface. As shown in Figure 3, the predominant data interface to smartphone cameras is the MIPI CSI-2 specification, based on the high-speed D-PHY or C-PHY physical layers operating at multi-Gbps data rates. While the formal MIPI Camera Control Interface (CCI) referenced by the CSI-2 specification is currently I2C (which is likely to be upgraded to reference I3C), in the absence of higher speeds available from I2C, SPI is often used for lower latency control functions including host-based active image stabilization. Another application requiring the higher speeds afforded by SPI is fast camera module initialization on power-up (boot) and dynamic firmware uploads to reconfigure the camera module. I3C is a reduced-pin interface candidate to replace the SPI in these cases and might also function concurrently as the CCI. Although two I3C interfaces are shown, these interfaces may be combined into one instance of I3C (as indicated by the dashed green line).

Low-speed camera data interface. While CSI-2 is used to transfer high resolution Gbps-rate pixel data to the host, low-resolution cameras generate Mbps-rate data and may be well served by I3C as opposed to many current uses of SPI. This may include the case of many low-resolution camera sensors connected on a common multi-point I3C bus to the host.

Figure 3: MIPI I3C in Camera Applications

Figure 3: MIPI I3C in Camera Applications

B. Touch controller interface. As shown in Figure 4, the predominant data interface for touch applications is currently SPI, where relatively higher 10-Mbps class speeds are needed, and I2C where lower 1-Mbps class speeds are needed. Here, data from an array of fine-pitched touch sensors located across the display panel capture the user or pen presses on the display for event transfers to the host. Different levels of processing are performed in the display panel and the host processor, but for most smartphones and similar class devices, I3C capability serves this application. INT and RESET signals may be absorbed as described earlier. In some applications one instance of I3C might suffice, such as with larger displays desiring multiple touch controllers, or in the camera case depending on requirements.

C. Audio codec interface. Per Figure 4, audio codecs exchange audio samples across various audio buses such as the MIPI SLIMbus and MIPI SoundWire. Analogous to how camera modules have rapid power-up and dynamic firmware transfer requirements, so can audio applications which include uploading audio templates to capture different languages, for example, and for which SPI is currently often used. Like the touch controller example, processing may be partitioned differently across codec and host and where data transfer latency is key. Similarly, INT and RESET signals may be absorbed as described earlier. The I3C interface may be used for these functions.

D. Near Field Communication (NFC) interface. Per Figure 4, a typical NFC system in smartphone applications is composed of two subsystems, the NFC controller (modem) and a secure element for security functions. For latency assurance or other reasons, each subsystem may use a dedicated SPI or I2C connection to the host. As before, these interfaces may be replaced by I3C, including its capability to consolidate the sideband signals in-band. System design considerations may require more than one I3C, or these interfaces may be combined (as indicated by the dashed green line).

Figure 4: I3C in Touch, Audio and NFC Applications

Figure 4: I3C in Touch, Audio and NFC Applications

Other Applications

Other applications of SPI are known in the industry; for brevity, we only describe two: use of SPI as a power management interface and low-resolution display interface.

Although MIPI has developed the System Power Management Interface Specification (SPMI) for power management control functions in mobile terminals, some implementations continue to use the older less efficient SPI or I2C interfaces, which can consider replacement by the more efficient I3C. Furthermore, its multi-point nature can be exploited to support the trend to separate power management across several integrated circuit chips in heat-constrained devices. As for displays, embedded applications requiring only low-resolution displays continue to use a variety of simple interfaces, including parallel data with strobes and SPI. These low-resolution SPI-based displays may also benefit from migration to I3C.

Conclusion

These identified application areas represent where the SPI may reasonably migrate to the MIPI I3C interface, driven by its performance and efficient pin-count including its sideband consolidation functions. However, closer examination of the I3C interface yields other benefits, including key energy savings relative to legacy interfaces by virtue of its modern and unique data signaling methods and lower cost connectors when these are needed. Finally, while the focus here has been on SPI migration to I3C, the migration to I3C will also occur for other established (legacy) interfaces, including the Universal Asynchronous Receiver/Transmitter (UART), discrete GPIOs for control functions, and of course the I2C interface on which MIPI I3C was built.


RickWietfeldtDr. Rick Wietfeldt serves as Chairman of the Technical Steering Group for MIPI Alliance whose mission is to drive MIPI’s technology roadmap, and as Sr. Director, Technology for Qualcomm Technologies Inc. where he leads the Advanced Connectivity Technology group. Dr. Wietfeldt holds a Ph.D. in Electrical Engineering, and is a well-known expert and spokesperson for technologies and trends in the mobile industry.

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