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Western Digital Introduces 512 Gigabit 64-Layer 3D NAND Chip

Western Digital Corp. has commenced pilot production of the company’s 512 Gigabit (Gb) three-bits-per-cell (X3) 64-layer 3D NAND (BICS3) chip in Yokkaichi, Japan, with mass production expected in the second half of 2017.

“The launch of the industry’s first 512Gb 64-layer 3D NAND chip is another important stride forward in the advancement of our 3D NAND technology, doubling the density from when we introduced the world’s first 64-layer architecture in July 2016,” said Dr. Siva Sivaram, executive vice president, memory technology, Western Digital.

The 512Gb 64-layer chip was developed jointly with the company’s technology and manufacturing partner, Toshiba. Western Digital first introduced initial capacities of the 64-layer 3D NAND technology in July 2016 and the 48-layer 3D NAND technology in 2015; product shipments with both technologies continue to retail and OEM customers.
Western Digital will present a technical paper on the advancement in high aspect ratio semiconductor processing that made this technology achievement possible on February 7 at the International Solid State Circuits Conference (ISSCC).

Contact Information

Western Digital


http://www.wdc.com/en/

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