IoT Design Needs New Components…Why Existing Embedded System Architectures Aren’t Good Enough

As connected embedded systems take care of increased data processing at the node, semiconductor memories must meet IoT performance and power demands.

When PC manufacturers were the largest consumer of semiconductor components, target specifications for IC manufacturers were dictated by the needs of the desktop computer. Energy consumption was not an issue, at least while the computer was plugged into an outlet. With the advent of laptops, cell phones and other mobile computing devices, extending battery life has become a primary focus, and semiconductor designs have undergone a major shift to accommodate more compact, energy efficient systems. The IoT represents yet another major re-think of embedded systems with reduction in energy consumption at an absolute premium.

This technology holds great promise for small embedded systems since it doesn’t suffer from the disadvantages of executing from on-chip embedded Flash or SRAM.

In the IoT world, we’re seeing smarter, more connected products, with new classes of IoT devices such as wearables, medical monitors, POS controllers and other connected embedded systems handling more data processing at the node itself. Of course this requires more program store, and given the size and power requirements of IoT, this can’t always be integrated into the chip.

Semiconductor memories are lagging far behind microcontrollers and other system components in making the grade, and current alternatives in the market cannot deliver on the performance and low power requirements of IoT devices.


The Need for a New Memory Architecture

Today, microcontroller (MCU) designers generally need to make a choice in memories. Use high-end DRAM that sits outside of a chip (and is large and expensive). Or integrate memory on chip at the low end (where space and power are limited). Because emerging IoT devices must handle more intelligent local data processing with associated higher levels of functionality, plus new wireless protocol stacks and advanced software, along with extremely limited battery power, neither of these solutions will work.

These mid-range products need more program memory than what can be implemented economically on-chip using embedded Flash or SRAM memory, and less than what is offered by the smallest DRAM devices. Until now, to hit performance targets, system designers have had to invest in memory solutions that are expensive, power-hungry, and performance limiting. What’s needed is a memory device that is tuned to sit outside of the chip and is affordable.
Enter eXecute-in-Place (XiP) Technology

Today’s eXecute-in-Place (XiP) technologies attempt to meet this challenge. With XiP, programs can be executed directly from long-term storage versus being copied into RAM. The architecture is designed to reduce the total overall memory required.

This technology holds great promise for small embedded systems since it doesn’t suffer from the disadvantages of executing from on-chip embedded Flash or SRAM. Unlike with embedded Flash, an MCU can be implemented with an external XiP solution using the latest process technologies, leading to better power consumption, higher frequency, and lower system cost. Unlike embedded SRAM, a XiP Flash device can be turned off, so it won’t consume any power during power-down modes. however, even state-of-the-art XiP solutions suffer from a lack of performance along with high power consumption and increased system cost.

Today’s XiP solutions present challenges in terms of limited performance, high power consumption, and the high cost needed to reach desired performance levels.

Adesto’s EcoXiP™, a new XiP non-volatile memory (NVM), in contrast, was designed from the ground up to be the optimal solution for serving as the main program memory in a XiP system. To create this novel solution, we needed to figure out how to build a chip that optimizes power, performance, and cost—not a small task!

Optimizing for Power

Systems that perform XiP are more sensitive to the power consumed during read operations than systems in which the Flash is used only during boot time, because the memory device must provide data to the MCU each time a “miss” occurs in the instruction cache. To address this, Adesto engineers optimized the power consumed in read operations.

Figure 2: Adesto EcoXiP performance. All numbers are for XiP operation and assume 16-byte instruction-cache lines and an average of 3.84 line fetches per instruction-cache miss. (Source: Adesto)

Figure 2: Adesto EcoXiP performance. All numbers are for XiP operation and assume 16-byte instruction-cache lines and an average of 3.84 line fetches per instruction-cache miss. (Source: Adesto)

Because IoT devices often have long periods of inactivity between system operations, we examined the tradeoffs between power savings and wake-up time, and provided multiple power down and standby modes in response. With an “ultra-deep” power down, the memory can standby in its lowest possible energy consumption state (200nA current). In addition, programmable I/Os for energy management can enable system designers to optimize the drive strength for each of the input and output channels on the memory device. Without this ability, memory designers must accommodate worst-case power requirements for longer leads to the device, wasting energy by supplying too much power on shorter lead lengths.

In most XiP systems, the MCU must stay awake during extended write operations so that it can power down the Flash after completing that operation. For IoT devices, this wakefulness wastes too much energy. The ability for the Flash to automatically power down after erase or write operations is key. Letting the MCU kick off the write operation and then automatically move into a low power mode while the Flash finishes its write operation means the MCU can be in power-down mode for an extra 5-10ms in program operations and up to a number of seconds in long erase operations. These extra seconds may not seem like a lot, but they certainly add up, and every bit of power savings is needed for IoT devices.

Optimizing for Performance

Most Flash memory chips use a quad Serial Peripheral Interface bus (SPI) to increase throughput while reducing pin count and cost. Other more expensive parts use an octal SPI for more sustained throughput. However, the throughput and latency for XiP operations still aren’t ideal. By extending the base SPI protocol to optimize for common access patterns, Adesto’s engineers doubled the bus throughput. The idea is that the EcoXiP continually provides sequential bytes until a new command is received—something we call “command fusing.”

Our team made other performance optimizations with typical IoT devices in mind. A concurrent “read-while-write” capability allows for over-the-air (OTA) updates and other data logging while read operations are executed. Other memory devices require consecutive execution of these functions, significantly affecting system performance. OTA updates on standard systems often require a second Flash memory device, adding considerable cost to the overall design.


As we enter the IoT era with many connected embedded systems handling more data processing at the node itself, we need more program storage, which can’t always be integrated on chip. For semiconductor memories to meet the combined performance and power requirements of the IoT, the industry needs a new approach to memory architectures for mid-range connected embedded systems.

With EcoXiP, Adesto designed a solution that builds on the benefits of XiP technology—including the ability to use the latest process technologies and to shut down to save power in power-down modes. We’ve overcome the drawbacks of other XiP solutions by taking a creative look at optimizations for power consumption and performance. This required a number of new features, and memory and protocol architecture. Improvements to the protocol itself were able to reduce the latency significantly—leading to a big impact on performance.

Adesto Technologies (NASDAQ:IOTS) is a leading provider of application-specific, ultra-low power non-volatile memory products. The company has designed and built a portfolio of innovative products with intelligent features to conserve energy and enhance performance, including Fusion Serial Flash, DataFlash®, EcoXiP™ and products based on Conductive Bridging RAM (CBRAM®). Contact Mr. Intrater at

AdestoGideonIntraterGideon Intrater is Adesto’s Chief Technology Officer. He brings more than 30 years of experience in the semiconductor market to his role in the company. Gideon serves on the Advisory board of Centipede Semi and Think Silicon and was previously a member of the advisory board of Sansa Security (acquired by ARM in July 2015). Previously, Mr. Intrater was Vice President of Marketing at MIPS Technologies (until the company was sold in February 2013). Before joining MIPS, Mr. Intrater was Vice President of Architecture for Symwave, a privately-held supplier of high-performance analog/mixed signal semiconductor solutions for consumer devices. Prior to Symwave, Mr. Intrater held various management positions at MIPS Technologies and National Semiconductor Corporation. Mr. Intrater holds over 30 issued patents. He earned BSEE and MSEE degrees from the Technion, Israel Institute of Technology, and an MBA from San Jose State University.

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