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Synopsys Delivers Industry’s First Multi-Protocol 25G PHY IP in 7-nm FinFET Process

Synopsys, Inc. announced its DesignWare Multi-Protocol 25G PHY IP for high-performance computing applications including machine learning and artificial intelligence. The PHY IP gives designers the flexibility to efficiently integrate multiple protocols including PCI Express 4.0, 25G Ethernet, SATA and CCIX into system-on-chips (SoCs) targeting the 7-nanometer (nm) and 16-nm FinFET processes.

The multi-protocol 25G PHY reduces power and area by more than 35 percent compared to the 16G PHY solution, incorporating optional power management features such as I/O supply under drive and decision feedback equalization (DFE) bypass. In addition, the programmable continuous calibration and adoption (CCA) feature optimizes performance across voltage and temperature variations, which is critical in harsh data center environments. Designers can integrate the multi-protocol 25G PHY with Synopsys’ digital controllers and verification IP for a complete, low latency, power-efficient IP solution that is compliant with the industry-standard protocol specifications.

“Globally, peak Internet traffic is projected to increase 4.6x from 2016 to 2020, a 36 percent CAGR, requiring semiconductors to incorporate new capabilities to meet high bandwidth demands of data center SoCs. The average number of IP blocks in these SoCs was 151 in 2016 and is projected to grow to 246 by 2020,” said Richard Wawrzyniak, principal analyst at Semico Research and Consulting Group. “Semico foresees the main enablers for high data rates to be high-speed SerDes solutions such as Synopsys’ new optimized DesignWare Multi-Protocol 25G PHY IP.”

DesignWare Multi-Protocol 25G PHY IP offers unique features to help designers meet their complex design requirements, including:
Flexible clock multiplier unit (CMU) including dual PLLs and dividers to support flexible multi-protocol configurations while transmitting high-quality data across lossy channels.

Performance analog front-end that incudes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE) for superior signal integrity and jitter performance.

Embedded bit error rate (BER) circuitry to efficiently evaluate channel quality, and on-die test features for testability and visibility into system performance, without requiring external test equipment.

Contact Information

Synopsys, Inc.

700 E. Middlefield Road
Mountain View, CA, 94043
USA

tele: 650.584.5000
www.synopsys.com

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