Semiconductor IP Survey 2017 Holds Surprises

CDT intellectual property (IP) survey highlights mixed signal, interface, fab, and third-party reuse trends.

By John Blyler, Editor-in-Chief, ESDE

The Chip Design Trends (CDT) annual semiconductor intellectual property (IP) summary details the trends in chip design, integration and manufacturing activities for 2016. A total of 193 filtered, technical professionals responded to this survey. Survey questions focused on IP market areas, categories, supplier selection, usage models, process geometries, foundries, design and integration issues and more.

Respondents represented a global audience with 68% from the USA, 19% from India and the rest distributed amongst Europe, Asia, Russia, and South America (see Figure 1).

Figure 1: Country of survey respondents.

Most of the IP supply chain was represented in over 170 companies as demonstrated by the wide range of respondents from AMD, Broadcom, Cisco Systems, Cogknit, Digitlog Technology, HPI, Intel, Mount Technology, Rockwell Collins, Sidence, STMicroelectronics, TI, and Toshiba.

I. Key Findings

* The largest market share for IP usage was shown to be consumer electronics and then communication networking. Automotive, Wearables/Smartphones/Tablets and Manufacturing usages followed somewhat distantly as the next major markets.

* In terms of IP usage, digital core IP took the lead followed by analog-mixed signal (AMS) IP. Memory IP was the third most used category of IP. Contrast these results to a 2013 CDT survey that placed memory IP significantly more popular than AMS IP. This increase in AMS IP is further supported by the growth of automotive electronics, wearable sensors and related signal conditions (see, “Mixed Signal and IoT Driving ASIC Design Starts Growth, says Semico Research”).

* More designers were using soft IP over hard IP. [Editor’s Note: Soft IP are cores that can be synthesized in a high-level language such as RTL, C++, Verilog, or VHDL and then incorporated into the place-and-route (P&R) design flow. Conversely, hard IP cores are low-level representations that cannot be modified by the chip designer.

* The leading use of IP for interface control and physical layer applications was USB followed in ranking by I2C, DDR, PCI/PCIe and AMBA AHB/APB/AXI.

* Somewhat surprisingly, most respondents didn’t find it particularly important to get all or most of their IP from one supplier (see Figure 2).

Figure 2: This chart shows a lack of importance in getting most of IP from one supplier.

* Most respondents didn’t contract with an ASIC or design services company. Those that did favored back-end design service companies.

* Not surprisingly, 28 to 45nm was the favored implementation process node followed by 55 to 65nm (see, “Moore’s Law has stopped at 28nm”)

* Regarding the foundries or IDMs used for IP designs, most respondents listed TSMC followed by Globalfoundries. In order, respondents also listed Samsung, IBM, SMIC and UMC.

*Three areas where the most IP integration time is spend include IP verification, followed by IP selection and IP integration. In future design efforts, respondents believe more time will be spent on die verification, mask generation and architectural verification.

* The most used third party IP vendor was ARM followed closely by Synopsys and then Cadence.  The next group in ranking was “Others,” which included in-house IP as well as a variety of vendors such as Xilinx, Altera, Intel, Broadcom and many small companies.

* The two most important IP integration design issues were meeting requirements and the quality of the documentation. Least was the third party vendor’s standing in the market.

* Most respondents estimated the corporate annual expenditure on IP was less than $100,000.

* Interestingly, more respondents have not yet decided whether their use of 3rd party IP will increase in 2016 and beyond (see Figure 3).

Figure 3: Many designers and manufactures uncertain as to their usage of third-party IP in the future.

 II. Implications

*Analog-mixed signal IP now rivals memory IP in usage in semiconductor chips. This result is confirmed by a recent report by Semico Research on IP Reuse (see Figure 4).

Figure 4: Growth in the types of IP blocks according to Semico Research (IP REUSE Conference, 2016).

Figure 4: Growth in the types of IP blocks according to Semico Research (IP REUSE Conference, 2016).

* Soft IP continues to outpace hard IP. This trend was predicted several years ago by Richard Wawrzyniak of Semico Research. He noted that for the Internet-of-Things applications, Soft IP would probably be used more often. He estimated that it could be as high as a 70 – 30 split in favor of Soft IP.” Designers should be cautious for while soft IP tends to be less expensive than hard IP, the former is also more difficult to secure in terms of IP theft.

This rise of both soft IP and AMS IP cores may seem counter-intuitive, as analog and mixed-signal logic tends to be used as Hard IP. However, the increased growth of soft IP is likely related to the continued dominance of processor-based digital IP, which holds a market share greater then AMS IP.

* The trend noted earlier – namely, the indifference of respondents in terms of getting all or most of their IP from one supplier – suggests that the IP market is still growing and open to new players. This is further supported by the large variety of IP companies listed as “other” in the category for third party IP usage.

* Semiconductor IP chips are experiencing integration issues in the manufacturing phase. This implication comes from that finding that most respondents favor back-end contract design service companies combined with the future design concerns of die verification, mask generation and architectural verification.

* The use of internal IP may on this rise, as potentially indicated by the response that more respondents have not yet decided whether their use of 3rd party IP will increase in 20

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