Improvement in QoR at Various Stages in Place and Route for 7nm Technology

By Vimar Gohel, Sr. Engineer, eInfochips – an Arrow Company

As we are moving towards lower geometry node, we face challenges in fitting multimillion gates with reduction of area. This results in high density/utilization of design. Therefore, starting utilization number is also becoming smaller i.e. we have to initialize design with lower gate density in such a way that the design becomes routable at the later stage of place and route cycle. Thus, placement density range is an important parameter to get a better QoR while routing design. While starting any chips designing process, placement density analysis can be very helpful to achieve better results even with less number of iterations.

In this paper, we will learn how to improve QoR at each stage in Place and Route.

P&R Stage: Placement

This is generally related to standard cell placement of design. When we are working at lowest geometry like 7nm, utilization of placed standard cells is very important in order to make the design routable.

Here are some of the ingredients from the recipe.

1. Cell padding for Flops, aoi, oai cells

If there is a dense congestion spot in the core area, it is possible that it is because of high pin density into a particular area. Here cell padding can be applied to those sequential or combinational cells which have a high number of pins.

For example,
specifyCellPad *_oa*  2
specifyCellPad *_ao*  2
specifyCellPad *dff* 2

2. Blockages between narrow macro channels

Macro-channel blockages can be implemented according to the logic spread. There will be a macro-channel as per the requirement of macro placement. Partial blockages can also be used to avoid extra logic to be seated into those channels to reduce congestion.

finishFloorplan -density 10 -fillPlaceBlockage partial 50 -namePrefix channel

P&R Stage: CTS (clock-tree synthesis)

There are various ways to fix timing at the CTS stage. The main difference in CTS is that all the clocks are built and routed in CTS design. Here are a couple of techniques to improve QoR:

1. Useful skew

Useful skew is a method of speeding up or slowing down the arrival of clock signals at the registered clock pins to fix setup violations. Innovus and EDI System can automatically utilize useful skew throughout the flow during the optimization and clock tree synthesis.


2. Integrated Clock-Gating (ICG) Cells

Clock gating is a technique to decrease the clock power by shutting off the clock to modules through a Clock Enable Signal. This functionally requires only an AND or OR gate. When using an AND gate with clock, the high EN edge may come anytime and may not coincide with a clock edge. In this case, the output of the AND gate will be 1 for lesser time duration than the clock’s duty cycle. This can, in turn, end up with a glitch in the clock signal.

To deal with this, one can use a special kind of clock gating cells that synchronize the EN with a clock edge. These are call-integrated clock gating cells or ICG.

In the latch-based clock gating technique, the cells add a level-sensitive latch to the design in order to hold the Enable Signal from the active edge to the inactive edge of the clock. This makes it unnecessary for the circuit to enforce that requirement. Since the latch captures the state of the Enable Signal and holds it until the complete clock pulse is generated, the Enable Signal needs to be stable only around the rising edge of the clock.

There are two commonly used ICG cell types:

P&R Stage: Routing

1. Skip Track

Skip Track option while doing Trial Route will also help in case the congestion is a bit on higher side.

Skip Track can be used from metal4 to metal10 with the ratio of 1:5.(this number can be user specific).

Skip Track option can be used while Trial Routing. Trail Route will skip 1 track at every 5 track to make detail route easier.

setTrialRouteMode -skipTracks “M4 1:5 M5 1:5 M6 1:5 M7 1:5 M8 1:5 M9 1:5 M10 1:5”


Placement Density range is concluded in this paper to have a better QoR.

  1. In case of higher memory count, the range can be 45% to 50%
  2. In case of moderate or no memory count, the range can be 55 to 60%

Once the placement density is defined, cell padding, macro channel blockages, skip tracking, uniform density, etc. are the options that can be used to have better QoR results after routing.

Check out the commonly asked questions related to physical design and verification methodologies.

Vimal Gohel is a senior physical design engineer, working at eInfochips for more than three years. He is holding an expertise in timing closure in 7nm technology. He is also having an extensive experience in back-end EDA tools & flow development in physical design. He has successfully taped out multiple projects in 16nm, 28nm, 40nm technologies.

Vimal has more than six years of experience and has worked with major semiconductor companies like ST Microelectronics, Cadence Design Systems during his professional career.

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