Has the Time Finally Arrived for SoC Level Verification IP?

Increasing System-on-Chip (SoC) complexity has led to IP verification challenges between architecturally different processors and interface cores. has confronted this challenge by offering a new SoC Verification IP category on its portal. To understand the importance of the move and its relationship to the upcoming Accellera Portable Stimulus standard, Semi-IP Systems talked with Steve Brown, Director of Product Marketing at Cadence. What follows is an edited version of our talk. – JB

Blyler: Traditional chip verification IP targets specific interfaces like USB or PCI. But ever-increasing SoC complexity requires system-level verification IP that includes processors, memories, interfaces and other resources. That’s a lot to cover. How has chip complexity affected verification IP?

Brown: Today’s verification IP is transactional, which means that it tells the user if transactions are being processed correctly. But the IP can’t tell if the transaction was expected. Verification should tell you if the interaction between different subsystems is being implemented as the customer expects. For example, consider the interaction of the Arm CPU with the PCI Express (PCIe) interface. PCIe came from the Intel world and has a completely different architectural paradigm to Arm CPUs. Chip designers have had to figure out how to make these two worlds can work together. (See Steve’s Blog: Arm meets Intel)

Blyler: This seems like a hardware IP design and implementation issue that complicates the verification activity. Why not just construct a clean interface from the PCIe subsystem to the Arm bus structure?

Brown: It’s not that easy. There are many interdependent touch points between the Arm CPU and PCIe subsystems. There are something like 4 or 5 parallel but interdependent control paths into the PCIe subsystem that must connect to the Arm CPU subsystem in a number of specific places. The whole concept of IP verification and verifying each IP with its interface protocol breaks down because a clean interface has not really been defined.

The need for low power provides an easy to understand example. Today’s SoCs can easily have hundreds of low power modes or states. To transition these chips into a specific power mode requires choreographing the power down of different subsystems in a particular order – all the while knowing than an interrupt can come at any time to redirect the system in another direction.

Blyler: How can you create a way to verify and test all these dynamic scenarios?

Brown: Creating tests for all of the different permutations is beyond what people can do today. The combinatorial size of all the test cases is bigger than a human team can accomplish. That is why the EDA community is using the concepts of constraints and randomization with a new language that describes systems in an abstract way to generate tests that cover all of those combinatorial spaces.

Blyler: You’re referring to the ongoing development of the portable stimulus (PS) standard.

Brown: Yes – The word portable comes from the fact that we are able to generate test that are executable on different verification engines – simulator, emulator, FPGA prototypes as well as post silicon boards.

Blyler: How does portable stimulus fit into’s new SoC verification category?

Brown: The goal is not to verify the existing ARM IP library but to verify the system scenarios involving the interface interactions with the Arm CPU subsystem. The portable stimulus standard will help users quickly generate tests, e.g., to ensure that cache coherent behavior in the CPU subsystems interacts properly with PCIe, USB, memory controller or other interface in the SOC. The capability will enhance the productivity of being able to specify, generate and further refine a list of tests – thanks to portable stimulus.

Verification IP must handle the entire System-on-Chip (SOC). (Courtesy of Cadence, ).

Of course, the official Accellera Portable Stimulus standard has yet to be approved. In the meantime, Cadence is providing a proprietary version that – we intend – will support the approved standard language. The standard will be ratified sometime this year (2018).

Thanks to the ecosystem, we (Cadence) have already received leads for our SoC verification IP.

Blyler: Thank you.

Originally Posted on “IP Insider.” Reprinted with permission.


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