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Q&A with Ted Marena, Microsemi

Accelerating positive change within the RISC-V landscape 

Editor’s Note: A May 2018 announcement by Microsemi of its collaboration with fabless semiconductor company SiFive, aimed at enabling Linux software and firmware developers to build RISC-V PCs, offered the opportunity to ask Ted Marena, director of FPGA/SOC business development  at Microsemi,  about the significance of the news to the embedded community. Edited excerpts follow.

EECatalog:  What are your best arguments for countering the opinion that RISC-V is not yet ready for prime time? 

Ted Marena, Microsemi: The momentum behind RISC-V is undeniable. Today the RISC-V Foundation has over 100 member organizations, and it is growing rapidly. Many of the members are tier 1 tech companies. At the most recent RISC-V conference in Barcelona, Spain, NXP, Google, and Western Digital all talked about how they are utilizing RISC-V. RISC-V brings benefits to both the software and hardware technical community. We’re seeing interest in using RISC-V for technologies such as storage controllers, performing management functions, or housekeeping, as embedded controllers on large SoCs, and vector extensions for machine learning.

Figure 1: Microsemi’s Mi-V Creative board is pre-programmed with a RISC-V core.

Further answering this question largely depends on what type of system you need to design. Here are three general classifications:

  1. If you are making a deeply embedded device, and you require a processor which is not exposed to end users, then RISC-V is ready for your design. Examples can be seen with both NVIDIA and Western Digital’s adoption of RISC-V;
  2. You need a device which is a microcontroller-based architecture. This design may need to run an RTOS or bare metal. The RISC-V ecosystem is well equipped to support these applications. You can obtain a 32-bit micro from SiFive or you can choose one of the Microsemi Mi-V RISC-V cores that fit in our FPGAs. The Mi-V ecosystem, which is part of our Accelerate Ecosystem, was created to support implementing soft RISC-V cores in Microsemi FPGAs. It consists of example designs, eval boards, an Eclipse-based IDE, and more. Microsemi has made it easy for firmware engineers to get started. We offer the Mi-V Creative board (Figure 1), which is pre-programmed with a RISC-V core and runs hello world out of the box. In addition, Mi-V cores are running open RTOS like FreeRTOS, MicroPython, Zephyr as well as commercial OS such as Micrium µC OSII and Express Logic’s ThreadX. These different RISC-V solutions are tailored for different applications. For example, some customers seek to incorporate multiple soft RISC-V cores in their FPGAs, while other users need floating point support. The Mi-V RISC-V ecosystem was created to address a broad range of such customer needs.
  3. If you are designing a system that requires Linux, the choices right now are a bit limited, but that is rapidly changing. Recently SiFive and Microsemi launched the Freedom Unleashed Expansion kit. This 2-board set has all the functionality of a RISC-V PC. The kit was developed to accelerate the growth of Linux based software, drivers, and middleware for RISC-V. The open-source community and many commercial organizations are now accelerating the development and upstreaming of RISC-V Linux software.

EECatalog:  How does the existence of Microsemi make the RISC-V landscape different than it would be if Microsemi did not exist?

Marena, Microsemi: More than three years ago Microsemi joined the RISC-V foundation as a platinum member because we believed in the power of innovation that could be realized. Several company members are involved in various committees. Ted Speers is on the board of directors, Ted Marena is the chair of the marketing committee, and several engineers participate in various technical task groups. From a market perspective Microsemi achieved two key milestones for RISC-V. First in November 2016, Microsemi announced the first RISC-V soft CPU for FPGAs. After this announcement we realized that more ecosystem growth was necessary. We began working on more CPUs, software tools, third-party tools and RTOSs, demo designs, boards, etc. When we achieved critical mass, we publicly announced our Mi-V RISC-V ecosystem in October of 2017. And to reiterate, most recently Microsemi and SiFive launched the Freedom Unleashed Expansion kit to accelerate the growth of the Linux-based RISC-V ecosystem.

EECatalog:  Why was it important to you to choose to spend time and effort participating in the DAC RISC-V Ecosystem Workshop?

Marena, Microsemi: The Linux-based Freedom Unleashed Expansion kit was released in May of 2018. We wanted to demonstrate that real applications could be run on Linux with RISC-V. Although we only had a month to create a solution, we implemented a deep learning core on our PolarFire FPGA with the SiFive U54 quad core running Linux. The deep learning core is from an IP company called Asic Design Services. They modified their design to work with RISC-V. We also had contributions from SiFive and Debian. This demo is a showcase for RISC-V as it used Debian Linux, Xserver, OpenCV, V4L drivers, PCIe drivers, and more. Microsemi continues to play a major role in RISC-V and we wanted to demonstrate for those attendees what is possible.

EECatalog:  How do RISC-V goals align with Microsemi’s customers’ goals?

Marena, Microsemi: Our FPGA products are unlike what the major FPGA vendors are doing. They are building the highest performance, fastest, largest devices they can to target the data center and hyperscale server market. Microsemi FPGAs are focused on the industrial, communications, and defense markets. For these applications, customers need their software to often run for decades and trust for security is also important. With RISC-V, the ISA is frozen. This means that any software that is written for RISC-V will run forever on any RISC-V core. Because the ISA is frozen, customers’  software investments are preserved. In other architectures, when new generations are released, instructions are normally added, and this requires re-compiling of the software. This is not the case with RISC-V. Because RISC-V is an open ISA, the design of the core can be provided to the customer. For example, Microsemi shares our soft RISC-V core RTL with customers. Because of this, customers can inspect our RISC-V core and establish trust. This is critical in security applications.

EECatalog:  What resources do you suggest for those wanting a deeper dive into RISC-V and security issues?

Marena, Microsemi: When one mentions security, it usually means very different things to different individuals. There are several member companies that offer security solutions based on RISC-V. Organizations such as SecureRF, Dover Microsystems, and Esperanto have solutions or are incorporating security features in their offerings. Recently RISC-V announced the formation of the Security Standing Committee to further secure the future of processing. Ted Speers from Microsemi deserves significant credit for elevating security to the highest levels for RISC-V. We are excited to have Rambus chair this critical group. For further specifics, head over to www.riscv.org.

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