IEDM 2018 Coming Up!

This is Part 1 of a multi-part blog series of previews of the upcoming IEDM 2018 conference.


On December 1st– 5ththe good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2018 IEEE International Electron Devices Meeting.  To quote the conference website front page, IEDM is “is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.”

That’s a pretty broad range of topics, but from my perspective, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years. Though these days process papers actually tend to be after the launch of the relevant product, such is the preoccupation with trade secrecy.

In the last few weeks I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order. However, at this point I need to confess that I have run short of time to finish this review so as to get it posted before the conference, so I have to break with tradition and skip a few of the sessions and papers that I will not be getting to. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.


Again this year the conference starts on the Saturday afternoon, with a set of six 90-minute tutorialson a range of leading-edge topics:

  • Emerging Device Technologies for Neuromorphic Computing, Damien Querlioz, CNRS
  • Reliability Challenges in Advanced TechnologiesRyan Lu, TSMC
  • Quantum Computing PrimerMark B. Ritter, IBM
  • Design-technology Co-optimization at RF and mmWave, Bertand Parvais, Imec
  • STT-MRAM Design and Device RequirementShinichiro ShiratakeToshiba Memory
  • Power Transistors in Integrated BCD Technologies, Hal Edwards, Texas Instruments

The first three are from 2.45 – 4.15, and the remainder from 4.30 – 6.00.

On Sunday December 2nd, we start with the short courses, “Scaling Survival Guide in the More than Moore Era” and “It’s All About Memory, Not Logic!!!”.

Last year the process short course was “Boosting Performance, Ensuring Reliability, Managing Variation in sub-5nm CMOS” so I guess we are now getting away from numbers, and the topics indeed show that:

  • Extreme-UV lithography – Principles, Present Status and OutlookTony Yen, ASML
  • MOSFET Scaling Knobs (GAA, NCFET…) and Future AlternativesWitek Maszara, GLOBALFOUNDRIES
  • Overcoming Variation ChallengesSivakumar Mudanai, Intel
  • 3D Integration for Density and FunctionalityJulien Ryckaert, imec
  • Advanced Packaging: the Next Frontier for Moore’s “Law”Subramanian Iyer, UCLA
  • Embedded Memory: Present Status, and Emerging Architecture and Technology for Future Applications, Eric Wang, TSMC

This year’s effort is organized by Jin Cai (TSMC). The memories session has been set up by Nirmal Ramaswamy of Micron, with the following sessions:

  • DRAM : Its Challenging History and FutureDong Soo Woo, Samsung
  • 3D Flash Memories: Overview of Cell Structures, Operations and Scaling ChallengesMakoto Fujiwara, Toshiba
  • Emerging Memories including Cross-Point, Opportunities and ChallengesKiran Pangal, Intel
  • Memory Reliability, Qualification and their Relation to System Level Reliability StrategiesTodd Marquart, Micron
  • Future of the Packaging Technologies for HBM, Nick (Namseog) Kim, SK Hynix
  • Processing in Memory (PIM): Performance and Thermal Challenges and OpportunitiesMircea Stan, University of Virginia

I would call both courses a full day, seeing as we finish at ~5.30 p.m., but it’s worth sticking around to the end.

If you have the stamina, at 5.30 CEA-leti is holding a Devices Workshopacross the street at the Nikko Hotel, discussing “Disruptive and Highly Secure Technologies for Data Management” and at6.00 imec is hosting a networking event  “Imec’s Tech Excellence and Belgian Beer & Gastronomy” at the Parc 55 hotel.


Monday morning, we have the plenary session, with three pertinent talks on the challenges and potential of contemporary electronics:

  • 4th Industrial Revolution and Foundry: Challenges and OpportunitiesEun Seung Jung, President of Foundry Business, Samsung Electronics

If we accept that the 3rd Industrial Revolution is our current era of information technology (computers, internet, etc.), then it is arguable that the 4th Industrial Revolution will be the fusion of the physical and cyber worlds (artificial intelligence, smart cars, homes, factories, etc).

In that context, we are likely to see larger than ever volumes of semiconductors being used, and this talk looks at the semiconductor ecosystem and the role of foundries in the 4th Industrial Revolution, the technological challenges involved, and possible solutions.

  • Venturing Electronics into Unknown Grounds,Professor Gerhard P. Fettweiss, Center for Advancing Electronics Dresden (cfaed), TU Dresden

cfaed is a German Cluster of Excellence located in Dresden, focused on stretching the limits of electronics into new territory. This presentation describes their methodology, combining horizontal research approaches with vertical studies of materials, devices, circuits and systems; and reviews the research topics of the center.

  • Future Computing Hardware for AI Jeff Welser, Vice President and Lab Director, IBM Research – Almaden

As we’ve seen at earlier IEDMs, hardware is being developed for artificial intelligence at both the chip and system level – neuromorphic memories, high-bandwidth CPUs, specialized AI accelerators, and high-performance networking gear. Dr. Welser will detail the hardware needs of AI, considering possible specialized technologies for AI, such as heterogeneous digital von Neumann machines, reduced-precision accelerator techniques, analog cores, and quantum computing.

Three quality presentations in three hours, but beware of numb bum if you take in all of them – get up and have a stretch in between, and take a walk before lunch!

After lunch, in keeping with IEDM’s tradition of intellectual overload, we have nine parallel sessions, and continuing this year – exhibitors, and coffee breaks to give us time to talk to them.

Session 2:Memory Technology – Charge Based Memories

Session 2 starts a track on Memory Technology, the first of four sessions. It begins with an invited paper by Intel/Micron on Scaling Trends in NAND Flash(2.1), updating us on 3D NAND, going from 32 to 64 and 96 layers, and 3 bits/cell to 4 bits/cell; and the problems involved for further scaling.

In 2.2Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory, Macronix investigates the operation of triple-level cell (TLC) and quad-level cell (QLC) charge-trap storage 3D NAND flash memories, concluding that random telegraph and program noise are the main influencers on the upper and lower Vt limits. A multi-times verify (MTV) scheme was tested and found to improve performance.

The authors in 2.3(Implementing Spike-Timing-Dependent Plasticity and Unsupervised Learning in a Mainstream NOR Flash Memory Array) report operating a mainstream NOR Flash array as an artificial synaptic array, demonstrating spike-timing-dependent plasticity (STDP) and unsupervised learning. Word-lines and bit-lines were pulsed to trigger hot-hole injection (HHI) or channel hot electron injection (CHEI) at the drain side of the cells in a conventional 40-nm double-polysilicon embedded technology.

Macronix is back again (2.4A Novel Voltage-Accumulation Vector-Matrix Multiplication Architecture Using Resistor shunted Floating Gate Flash Memory Device for Low-power and High-density Neural Network Applications) describing the use of a buried-channel shunt resistor added below floating gate flash memory cells, creating a neural network (NN) string from a string of flash cells. The weighting factors are stored in each flash cell, and the sum-of-product is obtained by summing the voltage drop of the cells in each string. Using flash technology, a high density NN array can be created within a processing-in-memory architecture.

We move into ferroelectrics next, with imec describing (2.5,Vertical Ferroelectric HfO2FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory) a vertical HfO2field effect transistor based on a 3D NAND-type structure. Up to 2 V memory window was achieved, and flash-like endurance of 1E4 cycles.

Next, a 10 nm node HfZrO based FE-FinFET device is demonstrated in 2.6Hybrid 1T e-DRAM and e-NVM Realized in One 10 nm node Ferro FinFET device with Charge Trapping and Domain Switching Effects, which showed both charge trapping and domain switching memory effects. In charge trapping mode, extreme high endurance (>1012), high operation speed (< 20 ns), good data retention (104@85C), and low operation voltage (<3 V) were identified, showing potential for e-DRAM. In domain switching mode, even better retention (>10 years) and read disturbance immunity were achieved, making eNVM a prospective use.

The last paper 2.7High-performance (EOT<0.4nm, Jg~10-7A/cm2) ALD-deposited RuSrTiO3stack for next generations DRAM pillar capacitor, is an imec study of a very high-k dielectric stack (k~118) for the next generation of DRAM, using a Ru\SrTiO3(STO)\Ru trilayer to form metal-insulator-metal (MIM) capacitors. An ultrathin cubic SrRuO3phase is formed at the Ru\STO bottom interface, optimizing the STO epitaxial quality of the dielectric layer. In addition to the high k-value, low leakage (10-7A/cm2at ±1V) was also obtained, making this an excellent candidate for compact pillar DRAM structures in the 1x-nm node range.

Session 3: Circuit and Device Interaction — Device and Algorithm Co-design for Neuromorphic and In-memory Computing

Paper 3.1,Exploiting Hybrid Precision for Training and Inference: A 2T-1FeFET Based Analog Synaptic Weight Cell, describes a 2-transistor-1FeFET based analog synaptic weight cell that exploits hybrid precision for in-situ training and inference. The modulated “volatile” gate voltage of the FeFET was used to represent the least significant bits for symmetric/linear update during training only, and the “non-volatile” polarization states of the FeFET to hold the information of most significant bits (MSBs) for inference.

Schematic of the proposed 2T1F weight cell design (3.1)

Next up (3.2) is an invited talk from IBM Research on Analog Computing for Deep Learning: Algorithms, Materials & Architectures, giving an overview of how nonvolatile memory (NVM) is used, and discussing what the NVM requirements are to give weight encoding a classification accuracy comparable to digital methods.

In 3.3Hardware Acceleration of Simulated Annealing of Spin Glass by RRAM Crossbar Array, a Ta2O5-based RRAM crossbar arrays and Cu-based CBRAMs were used to accelerate the solving of spin glass problems (N.B. not spin-on glass!). The RRAMs were utilized to calculate the Hamiltonian, and the CBRAMs for the decision of spin-flip events.

3.4Demonstration of Generative Adversarial Network (GAN) by Intrinsic Random Noises of Analog RRAM Devicesuses the noise generated by the write/read cycles of analog RRAM devices. The noise is the input of a neural network to improve the diversity of the generated numbers; the effect on the GAN performance was studied with a 1 kb RRAM array, and optimized  to moderate the influence of excessive noise.

The final paper in this session, 3.5Error-Resilient Analog Image Storage and Compression with Analog-Valued RRAM Arrays: An Adaptive Joint Source-Channel Coding Approachfrom Stanford/UCB, describes image storage and compression utilizing RRAM arrays; analog image data is directly stored onto an analog-valued RRAM array. A new joint source-channel coding algorithm was developed, together with a neural network, to encode and retrieve the images, and tolerant of variations in RRAM performance. A reconstruction performance is claimed of ~ 20 dB using only 0.1 devices/pixel for the analog image.

Session 4: Sensors, MEMS, and BioMEMS — Micro and Nano Electromechanical Systems

More folks from UCB start session 4 with a talk on digital ICs made from nano-electromechanical relays(4.1Demonstration of 50-mV Digital Integrated Circuits with Microelectromechanical Relays), reporting 50-mV operation at room temperature, allowing ultra-low active and zero static power consumption. The group used an electrostatic body-biased design with as few contacts as possible to reduce stiction effects, and a PFOTES (Perfluorooctyltriethoxysilane – had to look that up!) self-assembled monolayer molecular coating to reduce adhesion even further.

Yoshihiko Fuji of Toshiba will give an invited paper (4.2)on the use of spintronic strain-gauge sensors in a MEMS microphone, Highly sensitive spintronic strain-gauge sensor based on magnetic tunnel junction and its application to MEMS microphone. The sensors are based on magnetic tunnel junctions with an amorphous magnetostrictive sensing layer, giving gauge factors >5000.

4.3 Intermixing of motional currents in suspended CNT-FET based resonators; ETH Zurich examines the current generation in a suspended carbon nanotube field effect transistor (CNT-FET) resonators. This can have two components, conduction modulation and piezoresistive, and the ratio is dependent depends on gate bias and the asymmetry of the CNT-FET, affecting the frequency harmonics in nanoresonators.

One of the characteristics of graphene is the high temperatures it can tolerate. Case Western Reserve U. has studied tri-layer graphene nanoelectromechanical resonators (Glowing Graphene Nanoelectromechanical Resonators at Ultrahigh Temperature up to 2650K,4.4), controlling the Joule heating, they demonstrated ultra-wide frequency tuning up to Δƒ/ƒ ≈ 1300%, with corresponding temperature variation from 300 K up to 2650 K. When the temperature goes above 1800K, the devices start glowing and emitting visible light with solid mechanical resonance.

Paper 4.5from Columbia U. (Monolithic Integration of Micron-scale Piezoelectric Materials with CMOS for Biomedical Applications) describes the integration of piezoelectric materials with CMOS, aimed at biomedical use; polyvinylidene difluoride (PVDF) is used in medical implants, and lead zirconate titanate (PZT) for ultrasound imaging. Neither of these can tolerate conventional CMOS process temperatures, but the researchers achieved compatibility and preserved the piezoelectric properties of PVDF/PZT in micromachined ultrasonic transducers.

5G wireless is a hot topic these days, and the next paper (4.6,A Nano-Mechanical Resonator with 10nm Hafnium-Zirconium Oxide Ferroelectric Transducer) by Florida U. describes a 10-nm hafnium-zirconium oxide (HZO) layer that has been engineered to have the piezoelectric properties to resonate at ~4 MHz, enabling CMOS-compatible resonance at 5G frequencies.

A CNRS-led characterisation of optomechanical ring sensors formed on opto-SOI substrates (Comprehensive optical losses investigation of VLSI Silicon optomechanical ring resonator sensors) is presented in 4.7; the optical properties of a statistically significant sample size were investigated, giving excellent modelling to experiment agreement.

Session 5: Focus Session – Characterization, Reliability, and Yield — Interconnects to Enable Continued Scaling

The focus sessions consist of a series of invited papers on a specific topic; first up here (5.1)is Georgia Tech. with a review of the effects of different front-end devices (finFET, tunnel-FET etc.) on interconnect design (Interconnect Design and Technology Optimization for Conventional and Emerging Nanoscale Devices: A Physical Design Perspective), and the need for co-optimization between front- and back-ends.

IBM continues (5.2Mechanisms of Electromigration Damage in Cu Interconnects) with an examination of electromigration (EM) failure mechanisms in copper interconnects; they predict that the median lifetime of 7- or 10-nm node Cu with a TaN/Co liner and Co cap will be >10,000 years at 140oC with 1.5×107A/cm2current flow. Below 7-nm node there will be difficulties!

5.3Interconnect metals beyond copper: reliability challenges and opportunities, is an invited talk from imec on the reliability challenges of potential metals to replace Cu in future interconnects. The better oxidation resistance and higher cohesive energy of some metals could enable barrierless integration, if adhesion properties are optimized. Similarly a high melting point and slower self-diffusion kinetics could improve electromigration, making possible higher current capabilities.

Process challenges are metal etch vulnerability, potential voids, adhesion, CMP compatibility, obtaining high aspect ratio trench fill, and avoiding small grain pinning. Higher joule heating and mechanical stresses could cause delamination, and greater electromigration in nearby metal lines.

In 5.4Microstructure Evolution and Effect on Resistivity for Cu Nanointerconnects and Beyond, U. Texas investigates the evolution of microstructure with scaling in Cu, Co and Ru nano-interconnects and the effect on resistivity. Cu interconnects were studied down to 24 nm linewidths (14 nm node) with a high-resolution TEM precession microdiffraction technique. Monte Carlo simulation was also used to study grain growth in Cu, Ru and Co nano-interconnects, based on local energy minimization; and they examined the scaling effect on resistivity, also for Cu, Ru and Co, allowing for surface and grain boundary scatterings. The Cu and Co results agree with other published work.

Stanford U. looks at Integrating Graphene into Future Generations of Interconnect Wires(5.5), using single-layer graphene as the diffusion barrier and capping layer for Cu interconnects. With this structure, simulations of processor cores predict an 8% speed boost or 12% energy saving, and greater tolerance for process variations. The single-layer graphene is 3.35 Å thick, and provides 3.3× longer barrier lifetime than 2 nm TaN. Barrier reliability is expected to further improve with transfer-free and single-crystalline graphene. Cu electromigration lifetime is improved by 10× compared with Cu with 2 nm CoWP when in-situ low-temperature grown graphene (<0.7 nm thick) is used.

Multilayer graphene is also discussed as a potential Cu replacement, showing a better resistivity scaling trend with FeCl3doping, and better EM; and processor cores achieve 9% higher speed or 16% less energy consumption. EM lifetime of spin-on-glass encapsulated multi-layer graphene was twice that of than CoWP-capped Cu.

Applied Materials covers Interconnect Trend for Single Digit Nodes(5.6), now that we are in the 7-nm era and heading for the 5- and 3-nm nodes. New integration methods, materials, and fill technologies have to, and are, being studied.

Session 6: Focus Session – Nano Device Technology — Quantum Computing Devices

This topic is again covered by a set of research papers, but here we will only look at those dealing with qubits in Si technology. CEA-LETI reports on Si spin qubits in 6.2Towards scalable silicon quantum computing, considering the use of FDSOI to in-situ tune the devices using back bias.

6.3is a study of Qubit Device Integration Using Advanced Semiconductor Manufacturing Process Technology; it appears that qubits using semiconductor spin are similar to scaled transistors, so Intel has developed a qubit test chip on 300-mm wafers, using a28Si epitaxial layer to improve spin coherence. The quantum dots were created using a dual-nested gate integration process.

Keio U.discusses Silicon Isotope Technology for Quantum Computingin paper 6.4. Isotopically engineered Si-28/SiGe heterostructures were prepared for silicon-based quantum computers using a standard silicon CMOS integration technology. The Si-28 quantum wells were well-strained and showed high electron mobility and large valley-splitting, potentially allowing integration of Si spin qubits with CMOS circuitry.

Another CMOS-based strategy is described in 6.5,Scalable quantum computing with ion-implanted dopant atoms in silicon. Quantum information is encoded in the combined electron-nuclear spin state of individual ion-implanted phosphorus dopant atoms in silicon, enabling a qubit pitch of ~200 nm. Fast and high-fidelity quantum logic operations are predicted, and a potential “flip-flop” qubit system.

Session 7: Process and Manufacturing Technology — 3D Integration and Memory Technologies

3D integration in our industry has at least two interpretations – the stacking of completed chips in order to integrate multiple functions (so a form of packaging), and the monolithic stacking of transistors to create a single IC. In this session we have both!

imec starts off (7.1First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers) with the monolithic layering of finFETs, using junction-less devices in the top layer, and a 170nm wafer-bonding dielectric, fabricating and transferring them with processes ≤525ºC to avoid degradation. The local interconnect between the two layers was patterned with 193nm immersion lithography; the top layer was thin enough to allow this, enabling tight alignment precision of the top layer to the bottom layer (see below).

The top devices offer similar performance as the high temperature bulk finfet technology for low standby power applications. A TiN/TiAl/TiN/HfO2gate stack was adopted with La doping, giving good threshold voltage adjustment, reliability and low-temperature performance.

TEM cross-section of 3D stacked FinFETs along fins and across gates (7.1)

TEM cross-section of devices across fins with the gates covering the fins (7.1)

In 7.2, CEA-Leti continues to tell us about their CoolCube technology (Breakthroughs in 3D Sequential technology), which is the monolithic layering of planar transistors. One of the challenges of transistor stacking has been keeping the thermal budget for the top layer low enough to avoid degrading the bottom layer, and here we find out that a low resistance gate stack was formed using nanosecond laser processing, and a 500°C raised source & drain epitaxy was achieved. They also examined the intermediate Back End of Line properties (there is Cu/ULK under the top layer), and demonstrated the bonding of a Smart CutTMnm-thin wafer onto a CMOS wafer.

Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness(7.3) details a 3D-stacked CMOS image sensor from STMicroelectronics with a bonding pitch of 1.44 μm. The stacked hybrid bonding was progressed from 8 down to 1.44 μm without any specific failure mechanism due to pitch shrinkage.

We’ll have to pass on the memory papers, unfortunately, and sessions 8/9.

Session 8: Power Devices/ Compound Semiconductor and High-Speed Devices – Advances in Silicon Carbide and Gallium Oxide Silicon Power Devices

Session 9: Modeling and Simulation – Modeling and Simulation of Negative Capacitance Transistors

Session 10: Optoelectronics, Displays, and Imagers — Image Sensors

We have had stacked, hybrid-bonded image sensors in phones for a while, but the bonded connections have always been outside of the pixel array. In the first paper, 10.11.5μm dual conversion gain, backside illuminated image sensor using stacked pixel level connections with 13ke- full-well capacitance and 0.8e- noise, Omnivision takes the bonding into the array, and each pixel has a bonded connection.

We have a 1.5μm pixel size, 8 Mpixel, dual conversion gain (DCG), back-illuminated CMOS image sensor (CIS) with a linear full-well capacity (FWC) of 13ke- and total noise of 0.8e- RMS at 8x gain. The stacked pixel-level connection (SPLC) has the same 1.5μm pitch as the pixels, with >8M connections, maximizing the fill-factor of the photodiode and size of the associated transistor to achieve a large FWC and low noise performance at the same time. The allocation some of the cell read-out transistors into two different layers enables the DCG function to be fulfilled within the 1.5μm pixel size.

Sony reports (10.2A 0.68e-rms Random-Noise 121dB Dynamic-Range Sub-pixel architecture CMOS Image Sensor with LED Flicker Mitigation; the pixel has two sub-pixels of different sizes, allowing it to have ultra-low random noise of 0.68e-rms and a high dynamic range (HDR) of 121 dB in a single exposure, and mitigating LED flicker.

STMicroelectronics has developed a HDR Global Shutter (GS) pixel for automotive applications (10.4A HDR 98dB 3.2μm Charge Domain Global Shutter CMOS Image Sensor)with dual high-density storage nodes using Capacitive Deep Trench Isolation (CDTI). Pixel size is 3.2μm, claimed to be the smallest reported GS pixel with linear dynamic range of 98dB and noise floor of 2.8e-. The pinned memory isolated by CDTI can store 2 x 8000e- with dark current lower than 5e-/s at 60°C. A shutter efficiency of 99.97% at 505nm and a Modulation Transfer Function (MTF) at 940nm better than 0.5 at Nyquist frequency is also reported.

TowerJazz announces a 2.5um GS CIS pixel using an advanced Light-Pipe (LP) structure in 10.5(High Performance 2.5um Global Shutter Pixel with New Designed Light-Pipe Structure), reportedly the smallest GS pixel. The pixel has excellent Quantum Efficiency (QE), Angular Responses (AR) and very low Parasitic Light Sensitivity (PLS). These characteristics enable ultra-high resolution sensors, industrial cameras with wide aperture lenses, and low form factor optical modules for GS mobile applications.

Sony returns with 10.6Back-Illuminated 2.74 μm-Pixel-Pitch Global Shutter CMOS Image Sensor with Charge-Domain Memory Achieving 10k e- Saturation Signal. A 3208×2184 GS image sensor with back-illuminated architecture was fabbed in a 90 nm/65 nm imaging process. The sensor has 10000 electrons full-well capacity and -80 dB parasitic light sensitivity. Furthermore, 13.8 e-/s dark current at 60°C and 1.85 erms random noise are obtained. The pixel structure with memory, along with saturation enhancement technology is described.

That brings us to the end of the Monday afternoon sessions, and the reception will start at 6.30 pm in the Grand Ballroom.

Stay tuned for a preview of Tuesday’s sessions.

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