Real News
October - 2015
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- Imec and Cadence complete tapeout of first 5nm test chip
Nano-electronics research center imec and Cadence Design Systems, Inc. today announced that
September - 2015
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- GE Intelligent Platforms Sold to Veritas Capital
GE-IP to be âspun outâ to focus on rugged, COTS systems and positioned a notch or two removed from prime contractors.
August - 2015
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- Second DVCon India Kicks Off Soon
Last year the longtime USA-based Design and Verification Conference and Exhibition (DVCon) expanded to India for the first time. The debut DVCon India event was a major hit, drawing more than 450 attendees from more than 80 different companies and universities. This yearâs event will build on that success for an even bigger and better show, September 10-11 in Bangaloreâs stunning Leela Palace hotel.
- Comparison 1Y nanometer NAND architecture and beyond
A few years ago, some of the semiconductor process and device analysts thought 2D planar NAND
- "Contextual Sensing" is Another IoT Area for ARM
Convincing sensor vendors to add smarts to their devices and take a systems approach will provide context to IoT devices and give ARM two new growth areas.
- Computing at the Edge
As the number of devices at the edge of the network cloud continues to grow, more processing is needed to handle the huge quantities edge-connected data.
This is a collection of questions posed to ARM over the past couple of months; ARM's answersâattributed to the company's Ian Johnson, Senior Product Managerâare an excellent "quick read" ARM's recent IoT infrastructure initiative, and on Cortex-M7 processor. - Q&A with ARM: Securing the IoT using ARM Cortex Processors, and a growing mbed platform suite
ARMâs holistic approach to securing the IoT balances architecture, mbed OS and new software thatâs perfect for connected devices.
- Manage Giga-Gate Testing Hierarchically
The benefits of hierarchical test include reduction of test time, reduction of automatic test pattern generation (ATPG) run time, better management of design and integration tasks, and moving DFT insertion and pattern generation much earlier in the design process.
- USB Type-C: Doing Away with a Difference Makes a Difference
A connector technology that does away with a source of consumer frustration will invigorate
- The Odd Couple - Analog IPs and Design Data Management
Design engineers used to call mixed-signal chips âbig D/little Aâ for their high digital
July - 2015
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- It’s safety first at Embedded Systems Conference
Discussion of safety-critical technology became very timely this week at the Embedded Systems Conference Silicon Valley in Santa Clara, California, with the news about how security researchers were able to remotely take control of a Jeep Cherokeeâs systems, turning off the transmission and other functions.
- What Needs Re-imagining in the IoT Age and Why
Two industry veterans in position to offer informed perspectives on security, scalability,
- IoT, IP issues highlighted at Embedded Systems Conference
There are fun and serious sessions going on at the Embedded Systems Conference in Santa Clara, California.
- ITRS 2.0 Tackles System Level Integration
The International Technology Roadmap for Semiconductor (ITRS) has changed. It is no longer
- Breaking Down Power Management Verification
By Vijay Chobisa, Mentor Graphics Corporation For system-level power management verification,
June - 2015
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- Fuel for the Next Generation of Chip Design
Q&A with Silicon Cloud CEO Mojy Chian Goliaths, here come the Davids: How IoT is changing
- Improved Power Management with Sonics' ICE-Grain
Compared to conventional, software controlled approaches, Sonics' fine-grain hardware-controlled
- GHz Timing Giving You the Jitters? Three Things You Need to Know
Clock jitter can adversely affect high-speed protocols such as Ethernet, PCI Express and USB
- The Quest for Low Power
Lowering power consumption requires a holistic approach that touches every aspect of the design, from the transistors to the standard-cell building blocks, to the circuit architecture, and going all the way up to the application software running on the chip and system.
- Open-Silicon Wants Your Ideas for ASIC Designs
Founded in 2003, Open-Silicon has shipped more than 100 million application-specific integrated circuits in its history, according to Vasan Karighattam, the companyâs vice president of engineering with responsibility for architecture, system-on-a-chip design and verification, system software, and post-silicon validation.
- DAC Panel: Design Specialists Must Collaborate on Complex SoCs
A disgruntled designer of analog chips became the focal point of a Design Automation Conference panel session during lunchtime Wednesday.
- Accellera Panel: The Internet of Things Will Depend on Standards
Standards â the Internet of Things needs them. Most people agree on that. How IoT standards will be developed is up for grabs, according to panelists at a Tuesday morning session at the Design Automation Conference, held by the Accellera Systems Initiative.
- New EDAC Executive Director Looks to Revitalize Organization
âWe need to put more panache around EDA.â Thatâs Bob Smith, the new executive director of the EDA Consortium, speaking Tuesday afternoon at the Design Automation Conference.
- Blood and Tears at DAC: Why Google Thinks Smart Contacts Are Ideal for Diabetes Monitoring
At this yearâs Design Automation Conference (DAC) in San Francisco, Brian Otis, a Director at Google, talked about how hundreds of millions of people are at risk of diabetes â and how a smart contact lens that continuously monitors blood glucose levels and transmits the data to a smartphone might just be the ideal solution.
- Leti Launches Silicon Impulse FD-SOI Development Program
CEA-Leti announced that seven partners have joined its new FD-SOI IC development program, Silicon Impulse, launched to provide a comprehensive IC technology platform that offers IC design, advanced intellectual property, emulator and test services along with industrial multi-project wafer shuttles.
- Tackling Parameter Extraction for 16nm and Below
There are four reasons why parasitic parameter extraction is getting a lot harder for 16nm and below technology nodes: 1) 3D device geometries, such as the finFET, which result in more complex electrical fields around the device 2) multi-patterning, which causes increased variability; 3) a demand for 10X tighter levels of accuracy, and 4) increased levels of secrecy from foundries and designers.
- Move Over, 16nm: Here Comes 10nm Chips!
Those 16-nanometer chips with FinFETs? Yesterdayâs news. Taiwan Semiconductor Manufacturing wants you to know that theyâre ready, willing, and able to help you design chips with 10-nanometer features. The foundry presented at DAC with its long-time partners, ARM Holdings and Synopsys, on its preparations for the 10nm process node.
- Gary Smith: Should EDA Companies Look to Mechanical Design?
At the 2015 Design Automation Conference (DAC), analyst Gary Smith give his annual forecast and then made what might seem like a surprising suggestion. That the best way for EDA companies to grow might by acquiring mechanical design companies.
- MIPI D-PHY RX⁺: An Optimized Test Configuration
As MIPI® expands beyond the traditional mobile platform into safety sensitive applications,
- 2015 DAC Will Illuminate System Design Enablement Breakthroughs
Each Design Automation Conference (DAC) brings with it its own themes, most driven by recent commercial or academic technology developments, others driven by public announcements.
