April - 2016
- Optimizing Software Debug in Emulation
When debugging software on an emulator with a probe, something is always waiting. When the software developer is looking at memory, variables, and source code the emulator is occupied. With Codelink, most the waiting is eliminated as the developer interacts with a virtual target which is run on the same host as the debugger, eliminating the delays you get with a probe debugger. Because the virtual target is processing much less data than the original emulation, it can run faster â more than 10 times faster. This means 10 times less waiting for the developer. Download the paper to learn more.
February - 2016
- Delivering High Quality Analog Video Signals With Optimized Video DACs
In most modern consumer equipment, multimedia content is processed in the digital domain. However, analog video transmission requires the digital video content conversion to the analog domain. This white paper outlines the most common analog video signal standard-specifications that multimedia SoCs must support. It describes the key characteristics and features of a digital-to-analog converter solution optimized for video applications.
- Rapid Architectural Exploration in Designing Application-Specific Processors
Architectural exploration is at the heart of any ASIP design approach. This white paper explains the architectural tradeoffs available to an ASIP designer, such as performance vs. area, and why an ASIP design can still maintain full C-programmability while being optimized for a certain application domain.
- Addressing Three Critical Challenges of USB Type-C Implementation
As designers create new products and SoCs with USB Type-C support, they need to be aware of partitioning challenges. The SoC and system design must be partitioned to support the specificationâs requirements for precision analog circuitry plus high voltage/high current switches, and Type-C management software must be partitioned to execute on the processor, internal microcontroller, microcontroller in a power management IC, and/or on an external dedicated USB Type-C chip. This white paper describes key challenges and suggests solutions for designers of USB Type-C products and SoCs with native USB Type-C support.
- True Random Number Generators for Truly Secure Systems
Random numbers are at the heart of most security systems, yet methods for generating them vary in efficacy. Increasingly, many randomization algorithms and circuit implementations have been shown as flawed. This white paper examines current random number generation methods based on various entropy sources and associated attack techniques, including physical, statistical, and electronic methods.
- Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures
LPDDR4 offers huge bandwidth in a physically small PCB area and volume; up to 25.6 GByte/s of bandwidth at a 3,200 Mbps data rate from a single 15mmx15mm LPDDR4 package when two dies are packaged together. LPDDR4 builds on the success of LPDDR2 and LPDDR3 by adding new features and introducing a major architectural change. This white paper discusses why designers are selecting LPDDR4, how to handle 2-die and 4-die packages with multi-channel connections, the advantages of sharing channels through system-on-chip (SoC) partitioning, and how to optimize channels for the lowest power consumption.
- Designing an Efficient DSP Solution: Choosing the Right Processor and Software Development Toolchain
Read about key challenges in DSP implementation from both hardware and software application perspectives, and learn how a properly selected and configured DSP processor coupled with an advanced software development toolchain can overcome these challenges. This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specialized instruction-set architecture (ISA) coupled with a DSP-aware toolchain.
September - 2015
- Knock Out Designs Quickly With Layout vs Schematic Comparison
Manage performance, database size and accuracy before, during and after design. Download your free whitepaper to learn how the new Calibre nmLVS boxing capabilities help manage these trade-offs by allowing:
- Proper usage of regular, black and gray boxing options including strict hierarchy preservation on the black and gray boxed cells
- Management of IP, missing IP and incomplete blocks during design development
- Running of circuit verification and downstream processes ensuring IP and macro cell blocks hierarchy are not altered
June - 2015
- Using an Embedded Vision Processor to Build and Efficient Object Recognition System
The advent of high-performance mobile computing platforms is driving rapid progress in computer vision capabilities. Machine vision is becoming embedded in highly integrated SoCs and
May - 2015
- PCI Express 4.0 Controller Design and Integration Challenges
Designers need to start planning for PCI Express 4.0 integration now, because decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper
- Real-Time Trace: A Better Way to Debug Embedded Applications
Problems in the late phases of firmware and software development can be difficult to identify and debug, putting project schedules at risk. Learn how real-time trace hardware assistance
- Virtualizing Cloud Computing With Optimized IP for NFV SoCs
Growing internet traffic impacts how cloud and carrier data center operators design compute and data networking architectures. To meet demands for scale-out servers and networks, designers
April - 2015
- Ethernet in the Connected World
Read about the latest networking trends across some of the key market sectors including automotive, the connected home and data centers, and explains how Ethernet is relevant to each.
- Addressing IP Integration & Software Development Challenges to Accelerate SoC Time-to-Market
This white paper explores the issues facing SoC designers as they address SoC complexity and time-to-market challenges. High-quality IP alone is not enough with todayâs SoC complexity.
- A Method to Quickly Assess the Analog Front-End Performance in communication SoCs
Read about a method to determine if the electrical characteristics of any given AFE are adequate for the targeted application. Also, learn about a tool to explore tradeoffs between
- USB 3.1: Evolution and Revolution
This white paper digs into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the specification. USB 3.1 introduces a 10 Gbps signaling rate in addition to other features.
March - 2015
- On-chip Networks Optimize Shared Memory for Multicore SoCs
Performance of multicore SoCs is often dominated by external DRAM access, particularly in digital consumer devices running high quality video and graphics applications. Increasing core counts and newer DRAMs make the problems much more difficult. This article covers optimization of the on-chip network and memory system to achieve the required system throughput.
- High-Performance Analog and RF Circuit Simulation
The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Key challenges in the design of these circuits include block-level characterization and full-circuit verification. This paper highlights these verification challenges by discussing the results of a 2.2 GHz PLL LC-VCO, a 12-bit pipeline ADC, and an ultra-wideband transceiver.
- A Methodology for High-Speed Nanometer Transceiver Verification, Validation, and Characterization
This paper describes a new circuit validation and characterization flow that enables users to easily set up, run, record pass/fail, and analyze very complex tests. The validation and characterization flow was standardized across the design team, leveraging knowledge and computing resources and significantly improving design productivity.
- Efficient Noise Analysis for Complex Non-Periodic Analog/RF Blocks
This paper describes how AFS Transient Noise analysis enables circuit designers to efficiently perform SPICE-accurate device noise analysis on complex non-periodic analog/RF blocks. This capability enables designers to measure and optimize device noise analysis on complex blocks such as ADCs, frac-N PLLs, and int-N PLLs which would not otherwise have been possible without silicon iterations.
January - 2015
- Migrating Consumer Electronics to the Automotive World
Tough reliability standards for electronic automotive safety systems ensure that integrated circuits (ICs) comply with demanding performance and reliability requirements. These same IC reliability verifications tools can be used to validate circuit operation for "infotainment" and "connected car" applications, and ensure that customer reliability expectations are satisfied. Download your free report to learn how to: * Leverage existing IP for use in high-reliability applications * Provide automation for manual IC verification steps in your design flow * Improve existing coverage of IC reliability verification
December - 2014
- Implementing Flexible USB Type-C Control Using FPGA Technology
- Understanding Automotive Reliability and ISO 26262 for Safety Critical Systems
Automotive electronics play a critical role in today's automotive safety systems. While standards like ISO 26262 provide a framework for robust and reliable design and verification
November - 2014
- Analog Signal Conditioning for Accurate Measurements
Q: Should I put some sort of circuit between my sensor and an analog-to-digital converter?
A: Yes. You probably need some signal conditioning. The explanation below goes on for a bit, but stay with it and you'll understand what you need and why you need it.
- USB 3.1: Evolution and Revolution
USB-IF Worldwide Developers Days introduced developers to the new USB 3.1 specification. This white paper digs deep into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the specification.
September - 2014
- 7 Key Considerations For Effective Chip-Package Thermal Co-Design
Chip-package co-design is important for several reasons. Designing a large high power die, e.g. a System-on-Chip (SoC) without considering how to get the heat out is likely to lead
July - 2014
- Ultra Low-Power 9D Sensor Fusion Implementation: A Case Study
Today, the ability to track the orientation or position of a device is a common feature in many portable and wearable products. Computing the orientation is a non-trivial task that
June - 2014
- 12 Key Considerations in Enclosure Thermal Design… A High-Level ‘How To’ Guide
A natural focus when designing electronics products are, well the electronics. The electronics itself however, needs to work within some kind of enclosure, and must be designed with the enclosure in mind. Cooling is a system issue, which is why we advocate a top-down approach, starting at the enclosure level.
- 10 Tips for Streamlining PCB Thermal Design… A High-Level ‘How To’ Guide
Many aspects of a PCBâs performance are determined during detailed design. Thermal issues with the PCB design are largely âlocked inâ during the component (i.e. chip package)
- 10 Tips for Predicting Component Temperatures… A High-Level ‘How To’ Guide
Recently, physics-based reliability prediction has related electronic assembly failure rates to the rate and magnitude of temperature change over an operational cycle, both of which are influenced by steady-state operating temperature. Whether the intention is to increase reliability, or improve performance, accurate prediction of component temperatures helps meet design goals.