May - 2015
- PCI Express 4.0 Controller Design and Integration Challenges
Designers need to start planning for PCI Express 4.0 integration now, because decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper
- Virtualizing Cloud Computing With Optimized IP for NFV SoCs
Growing internet traffic impacts how cloud and carrier data center operators design compute and data networking architectures. To meet demands for scale-out servers and networks, designers
- Real-Time Trace: A Better Way to Debug Embedded Applications
Problems in the late phases of firmware and software development can be difficult to identify and debug, putting project schedules at risk. Learn how real-time trace hardware assistance
- Rapid Architectural Exploration in Designing Application-Specific Processors
Application-specific processors deliver high performance and energy efficiency with flexibility to address late specification changes and post-silicon modifications. Learn how Synopsysâ
April - 2015
- Ethernet in the Connected World
Read about the latest networking trends across some of the key market sectors including automotive, the connected home and data centers, and explains how Ethernet is relevant to each.
- Addressing IP Integration & Software Development Challenges to Accelerate SoC Time-to-Market
This white paper explores the issues facing SoC designers as they address SoC complexity and time-to-market challenges. High-quality IP alone is not enough with todayâs SoC complexity.
- A Method to Quickly Assess the Analog Front-End Performance in communication SoCs
Read about a method to determine if the electrical characteristics of any given AFE are adequate for the targeted application. Also, learn about a tool to explore tradeoffs between
- USB 3.1: Evolution and Revolution
This white paper digs into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the specification. USB 3.1 introduces a 10 Gbps signaling rate in addition to other features.
March - 2015
- On-chip Networks Optimize Shared Memory for Multicore SoCs
Performance of multicore SoCs is often dominated by external DRAM access, particularly in digital consumer devices running high quality video and graphics applications. Increasing core counts and newer DRAMs make the problems much more difficult. This article covers optimization of the on-chip network and memory system to achieve the required system throughput.
- High-Performance Analog and RF Circuit Simulation
The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Key challenges in the design of these circuits include block-level characterization and full-circuit verification. This paper highlights these verification challenges by discussing the results of a 2.2 GHz PLL LC-VCO, a 12-bit pipeline ADC, and an ultra-wideband transceiver.
- A Methodology for High-Speed Nanometer Transceiver Verification, Validation, and Characterization
This paper describes a new circuit validation and characterization flow that enables users to easily set up, run, record pass/fail, and analyze very complex tests. The validation and characterization flow was standardized across the design team, leveraging knowledge and computing resources and significantly improving design productivity.
- Efficient Noise Analysis for Complex Non-Periodic Analog/RF Blocks
This paper describes how AFS Transient Noise analysis enables circuit designers to efficiently perform SPICE-accurate device noise analysis on complex non-periodic analog/RF blocks. This capability enables designers to measure and optimize device noise analysis on complex blocks such as ADCs, frac-N PLLs, and int-N PLLs which would not otherwise have been possible without silicon iterations.
January - 2015
- Migrating Consumer Electronics to the Automotive World
Tough reliability standards for electronic automotive safety systems ensure that integrated circuits (ICs) comply with demanding performance and reliability requirements. These same IC reliability verifications tools can be used to validate circuit operation for "infotainment" and "connected car" applications, and ensure that customer reliability expectations are satisfied. Download your free report to learn how to: * Leverage existing IP for use in high-reliability applications * Provide automation for manual IC verification steps in your design flow * Improve existing coverage of IC reliability verification
December - 2014
- Implementing Flexible USB Type-C Control Using FPGA Technology
- Understanding Automotive Reliability and ISO 26262 for Safety Critical Systems
Automotive electronics play a critical role in today's automotive safety systems. While standards like ISO 26262 provide a framework for robust and reliable design and verification
November - 2014
- Analog Signal Conditioning for Accurate Measurements
Q: Should I put some sort of circuit between my sensor and an analog-to-digital converter?
A: Yes. You probably need some signal conditioning. The explanation below goes on for a bit, but stay with it and you'll understand what you need and why you need it.
- USB 3.1: Evolution and Revolution
USB-IF Worldwide Developers Days introduced developers to the new USB 3.1 specification. This white paper digs deep into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the specification.
September - 2014
- 7 Key Considerations For Effective Chip-Package Thermal Co-Design
Chip-package co-design is important for several reasons. Designing a large high power die, e.g. a System-on-Chip (SoC) without considering how to get the heat out is likely to lead
July - 2014
- Ultra Low-Power 9D Sensor Fusion Implementation: A Case Study
Today, the ability to track the orientation or position of a device is a common feature in many portable and wearable products. Computing the orientation is a non-trivial task that
June - 2014
- 12 Key Considerations in Enclosure Thermal Design… A High-Level ‘How To’ Guide
A natural focus when designing electronics products are, well the electronics. The electronics itself however, needs to work within some kind of enclosure, and must be designed with the enclosure in mind. Cooling is a system issue, which is why we advocate a top-down approach, starting at the enclosure level.
- 11 Top Tips for Energy-Efficient Data Center Design and Operation… A High-Level ‘How To’ Guide
Data center power load (and therefore heat dissipation) footprints continue to rise in response to growing demand for information storage and transfer. Cooling constitutes a major cost in the operation of a data center which has led to increased focus on minimizing energy use in data centers.
- 10 Tips for Predicting Component Temperatures… A High-Level ‘How To’ Guide
Recently, physics-based reliability prediction has related electronic assembly failure rates to the rate and magnitude of temperature change over an operational cycle, both of which are influenced by steady-state operating temperature. Whether the intention is to increase reliability, or improve performance, accurate prediction of component temperatures helps meet design goals.
- 10 Tips for Streamlining PCB Thermal Design… A High-Level ‘How To’ Guide
Many aspects of a PCBâs performance are determined during detailed design. Thermal issues with the PCB design are largely âlocked inâ during the component (i.e. chip package)
May - 2014
- The truth about knowing your False Paths
ASIC and & FPGAs have many false paths that implementation tools attempt to optimize to make timing goals. Adding false path constraints frees up the synthesis tool to work only on necessary paths. Blue Pearl automates false path generation that can be run after design changes
- Reduce Metastability by Using a User Grey Cell™ Methodology for IP and FPGA Clock Domain Crossing Analysis
This paper introduces a novel technique for Intellectual Property (IP) and FPGA clock domain crossing (CDC) analysis using Blue Pearlâs User Grey Cellâ¢ methodology rather than the traditional Black Box methodology.
March - 2014
- Disruptive New Serial-Interface; Intelligent Memory Architecture Jumps 100/400GbE Performance Wall
Packet processor design teams face increasingly difficult challenges as they seek to provide their network equipment manufacturers with state-of-the-art devices. The interrelated system-level trade-offs include performance, pin count, and area, and are all ultimately limited by power consumption considerations. To successfully compete, network chip vendors must consider end-to-end solutions for system architects and developers. In turn, as OEMs introduce multi-terabit systems, they must aggregate multiple 100 Gbps ports on each line card or risk falling behind the performance curve.
August - 2013
- An FPGA Approach to Implementing Time-Critical Functions in Multi-Sensor Mobile Designs
An FPGA Approach to Implementing Time-Critical Functions in Multi-Sensor Mobile Designs.
September - 2012
- Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller
Taking full advantage of the performances of the 7 Series FPGAs can be done by using the high speed memory controller from Barco Silex, which has been reworked to achieve the highest frequency and efficiency.
June - 2012
- Enea Element®: Simplify Distributed Systems with Frameworks from Enea Element
Distributed systems range from simple multi-threaded applications to multi-slot chassis-based systems to networked clusters of servers. Topologies get more complex when these systems move into cloud-based environments, and more diverse when they involve machine-to-machine (or M2M) solutions. Providers of distributed system software solutions face a number of challenges in building, debugging and maintaining a set of connected applications. Managing these systems requires powerful modeling and a variety of management interfaces to meet a diverse set of needs. The services provided by a distributed system often require a high level of availability. The middleware frameworks that make up Enea Element address many of these challenges.
May - 2012
- Write Assist in Low-Voltage SRAMs
Write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. One of the key reasons to push the SRAM Vmin lower is to enable efficient Dynamic Voltage and Frequency Scaling (DVFS) to save power. In this paper, we discuss the basics of SRAM faliure mechanisms, fundamentals of write assist techniques, ARMÂ® ArtisanÂ® Low Voltage Memory Compilers with the write assist feature and results from GLOBALFOUNDRIES 28nm-SLP memories.