January - 2013

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• FPGA & PLD
  SmartFusion2 Lowest Power FPGAs

  The SmartFusion®2 system-on-chip (SoC) FPGA is differentiated from other FPGAs by its low power capabilities that enable orders of magnitude lower power operation for low duty cycle applications.

September - 2012

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• Chip Design
  Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller

  Taking full advantage of the performances of the 7 Series FPGAs can be done by using the high speed memory controller from Barco Silex, which has been reworked to achieve the highest frequency and efficiency.

July - 2012

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• Chip Design
  Write Assist in Low-Voltage SRAMs

  Write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. One of the key reasons to push the SRAM Vmin lower is to enable efficient Dynamic Voltage and Frequency Scaling (DVFS) to save power. In this paper, we discuss the basics of SRAM faliure mechanisms, fundamentals of write assist techniques, ARM® Artisan® Low Voltage Memory Compilers with the write assist feature and results from GLOBALFOUNDRIES 28nm-SLP memories.

June - 2012

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• Multicore
  Enea Element®: Simplify Distributed Systems with Frameworks from Enea Element

  Distributed systems range from simple multi-threaded applications to multi-slot chassis-based systems to networked clusters of servers. Topologies get more complex when these systems move into cloud-based environments, and more diverse when they involve machine-to-machine (or M2M) solutions. Providers of distributed system software solutions face a number of challenges in building, debugging and maintaining a set of connected applications. Managing these systems requires powerful modeling and a variety of management interfaces to meet a diverse set of needs. The services provided by a distributed system often require a high level of availability. The middleware frameworks that make up Enea Element address many of these challenges.
• RF and Microwave Systems
  Redefining RF and Microwave Instrumentation Through Open Software and Modular Hardware

  National Instruments uses multicore processors, user-programmable FPGAs, the high-throughput PCI Express system bus in PXI, and LabVIEW graphical system design software to address the business and technology challenges of high-frequency test and measurement. Read the white paper.

May - 2012

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• Military & Aerospace
  VPX for High-Performance Avionic Computers

  Traditional high-performance computing platforms are limited by the connection bandwidth and latency between the multiple computing elements needed to achieve the performance targets. For the embedded market, the difficulty is compounded by the demanding environmental requirements. The VPX standard resolves this limitation with a large number of high-throughput point-to-point connections between the processing elements in a rugged mechanical structure.
• Multicore
  OpenVPX System Bandwidth: A comparison of 10Gb Ethernet Performance, Serial Rapid IO, and InfiniBand

  This paper compares the bandwidth available to two common types of dataflow for systems based on the VITA 65 CEN16 central switched topology, using three different fabrics – Serial RapidIO (SRIO), 10 Gigabit Ethernet (10GbE), and Double Data Rate InfiniBand (DDR IB).
• FPGA & PLD
  Xilinx 7 Series FPGAs: The Logical Advantage

  Configurable logic tiles are the fundamental building blocks of all programmable digital electronic systems. Ever since Xilinx invented the FPGA in the 1980s, configurable logic, in the form of look-up tables and registers, has been an essential component of digital electronics systems across all markets and applications. This white paper describes the features of the configurable logic block in the 28 nm Xilinx 7 series FPGAs, highlighting advantages over previous Xilinx FPGAs and the benefits that these changes bring to the digital design engineer.

February - 2012

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• Chip Design
  LTE-Advanced Signal Generation and Measurement Using SystemVue

  LTE-Advanced is specified as part of Release 10 of the 3GPP specifications and is now approved for 4G IMT-Advanced. This application note introduces key LTE-Advanced techniques, as well as how to use the Agilent SystemVue W1918 LTE-Advanced library to generate various downlink (DL) orthogonal frequencydivision multiple access (OFDMA) and uplink (UL) clustered DFT-spread-OFDM (DFT-S-OFDM) signal sources with MIMO, and to measure closed-loop throughput.

  This application note also introduces LTE-Advanced enhancements to the MIMO channel models, which are available as simulation model set called the W1715 SystemVue MIMO channel builder. This optional model set facilitates simulation-based MIMO over-the-air (OTA) testing using real, observed antenna patterns and standard MIMO fading models, and overcomes a key challenge for 8-layer MIMO system analysis and verification.

August - 2011

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• Medical Electronics Design
  Best Practice Development Processes for Medical Device FPGAs

  For FPGA developers working on designs for medical devices, one approach to dealing with regulatory uncertainty is to borrow heavily from design assurance processes in other safety-critical industries, such as avionics, where standards are well established. These well-established standards mandate a development flow that is controlled, auditable and perhaps most important, specific to the requirements of hardware engineering. While following such a flow will not guarantee smooth sailing though every regulatory approval process for FPGA devices bound for medical applications, it is consistent with basic regulatory intent - to demonstrate to auditors that complex devices meet their requirements and perform well under all foreseeable conditions.

May - 2011

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• Chip Design
  Direct Power MOSFET Capacitance Measurement at 3000 V

  Learn how to make power MOSFET capacitance measurements at up to 3000 V of DC bias.
• Chip Design
  Common Pitfalls in PCI Express Design

  PCI Express is a point-to-point communications interface. It is neither an evolved nor enhanced form of PCI or PCI-X, but, essentially, a high speed, low voltage, differential serial pathway for communication between two devices, although it uses the same programming model as its predecessors.

April - 2011

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• Chip Design
  Increasing Revenue Through Continuously Optimized Data Center Management

  Most businesses are completely dependent on technology, and the impact of using non-optimized technology can be directly measured in their revenue. Why? Because as widespread dependence on technology has grown, the size and complexity of the technology’s environment has grown in a non-linear manner.

January - 2011

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• FPGA & PLD
  Designing For Low Power

  Power consumption is becoming an increasingly important variable when it comes to calculating OPEX and carbon footprint for telecom infrastructure projects.

November - 2010

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• Chip Design
  10 Reasons to Customize A Processor Core

  There are plenty of really good, proven processor cores on the market today. But if you have more than simple control tasks, perhaps you’ve considered using a processor that you can customize. We’ll give you 10 good reasons why you should consider customizing your core in your next SOC design.
• Chip Design
  The What, Why, and How of Customizable Dataplane Processors (DPUs)

  Designers have long understood how to use a single processor for the control functions in a SOC design. However, there are a lot of data-intensive functions that control processors cannot handle. That’s why designers design RTL blocks for these functions. However, RTL blocks take a long time to design and even longer to verify, and they are not programmable to handle multiple standard or designs.
• Chip Design
  Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC

  Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC [company]
• Chip Design
  Cut DSP Development Time – Get High Performance From C, No Assembly Required

  Cut DSP Development Time – Get High Performance From C, No Assembly Required [company]
• Chip Design
  Get Your ASICs and SOCs Off the Bus!

  Get Your ASICs and SOCs Off the Bus! [company]
• Chip Design
  The Five Pitfalls of 4G Baseband SOC Design

  The Five Pitfalls of 4G Baseband SOC Design [company]

October - 2010

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• Chip Design
  Silicon On Insulator (SOI) Implementation

  Increased demand for high performance, low power and smaller area among microelectronic devices is continuously pushing the fabrication process to go beyond ultra-deep sub-micron (UDSM) technologies, leading to an alternative, Silicon On Insulator (SOI) process. The paper introduces SOI technology, talks about the design challenges associated with ASIC implementation with SOI for today’s complex designs and finally lists out implementation guidelines to overcome these challenges.

June - 2010

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• Chip Design
  Creating Multi-Time-Domain ATE Test Programs for SOC Device Designs

  Modern chip designs frequently involve System-on-Chip architectures as ever increasing levels of integration brings more functionality on board. One of the ramifications of this increased system integration is increasingly complex clock schemes throughout the chip. In the best case scenario, clock trees distribute clock signals from common points to all the synchronous functional elements on the chip and often include simple dividers to create the specific frequencies required by each function block.

May - 2010

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• Multicore
  The Significance of Intel’s Core i7 to Embedded Computing

  At the Consumer Electronics Show (CES) on January 7, 2010, Intel® announced 27 new processors in its Core® i3, Core® i5 and Core® i7 families. Significantly for the embedded industry, twelve of these were targeted specifically at embedded applications. Early indications are that the Core i7 will offer either more processing performance per watt compared with earlier products (estimated at around 20%), or lower power consumption per unit of processing performance than its predecessors.

October - 2009

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• Chip Design
  Evolving the Coverage-driven Verification Flow

  Verification methodology has undergone dramatic changes over the past decade. The realization that larger and more-complex designs required more and more verification effort, coupled with shrinking schedules, spawned new languages specifically tailored for verification and tools intended to make the verification process more predictable and efficient.

April - 2009

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• Chip Design
  The PSP Model in RF CMOS Design

  This white paper explains the technology behind Penn State Philips (PSP) transistor models and how they relate to actual device behavior.