September - 2014
- 7 Key Considerations For Effective Chip-Package Thermal Co-Design
Chip-package co-design is important for several reasons. Designing a large high power die, e.g. a System-on-Chip (SoC) without considering how to get the heat out is likely to lead
July - 2014
- Ultra Low-Power 9D Sensor Fusion Implementation: A Case Study
Today, the ability to track the orientation or position of a device is a common feature in many portable and wearable products. Computing the orientation is a non-trivial task that converts inputs from multiple motion sensors into accurate position information. This computation is called sensor fusion and it eliminates inaccuracies from noisy sensor inputs. This paper shows how using DesignWare® ARC® Processor EXtension (APEX) technology improves cycle count and energy consumption for a power-efficient implementation of a 9D fusion algorithm on an IP subsystem.
June - 2014
- 10 Tips for Streamlining PCB Thermal Design… A High-Level ‘How To’ Guide
Many aspects of a PCB’s performance are determined during detailed design. Thermal issues with the PCB design are largely ‘locked in’ during the component (i.e. chip package)
- 10 Tips for Predicting Component Temperatures… A High-Level ‘How To’ Guide
Recently, physics-based reliability prediction has related electronic assembly failure rates to the rate and magnitude of temperature change over an operational cycle, both of which are influenced by steady-state operating temperature. Whether the intention is to increase reliability, or improve performance, accurate prediction of component temperatures helps meet design goals.
- 12 Key Considerations in Enclosure Thermal Design… A High-Level ‘How To’ Guide
A natural focus when designing electronics products are, well the electronics. The electronics itself however, needs to work within some kind of enclosure, and must be designed with the enclosure in mind. Cooling is a system issue, which is why we advocate a top-down approach, starting at the enclosure level.
- 11 Top Tips for Energy-Efficient Data Center Design and Operation… A High-Level ‘How To’ Guide
Data center power load (and therefore heat dissipation) footprints continue to rise in response to growing demand for information storage and transfer. Cooling constitutes a major cost in the operation of a data center which has led to increased focus on minimizing energy use in data centers.
May - 2014
- Reduce Metastability by Using a User Grey Cell™ Methodology for IP and FPGA Clock Domain Crossing Analysis
This paper introduces a novel technique for Intellectual Property (IP) and FPGA clock domain crossing (CDC) analysis using Blue Pearl’s User Grey Cell™ methodology rather than the traditional Black Box methodology.
- The truth about knowing your False Paths
ASIC and & FPGAs have many false paths that implementation tools attempt to optimize to make timing goals. Adding false path constraints frees up the synthesis tool to work only on necessary paths. Blue Pearl automates false path generation that can be run after design changes
March - 2014
- Disruptive New Serial-Interface; Intelligent Memory Architecture Jumps 100/400GbE Performance Wall
Packet processor design teams face increasingly difficult challenges as they seek to provide their network equipment manufacturers with state-of-the-art devices. The interrelated system-level trade-offs include performance, pin count, and area, and are all ultimately limited by power consumption considerations. To successfully compete, network chip vendors must consider end-to-end solutions for system architects and developers. In turn, as OEMs introduce multi-terabit systems, they must aggregate multiple 100 Gbps ports on each line card or risk falling behind the performance curve.
August - 2013
- An FPGA Approach to Implementing Time-Critical Functions in Multi-Sensor Mobile Designs
An FPGA Approach to Implementing Time-Critical Functions in Multi-Sensor Mobile Designs.
September - 2012
- Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller
Taking full advantage of the performances of the 7 Series FPGAs can be done by using the high speed memory controller from Barco Silex, which has been reworked to achieve the highest frequency and efficiency.
July - 2012
- Write Assist in Low-Voltage SRAMs
Write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. One of the key reasons to push the SRAM Vmin lower is to enable efficient Dynamic Voltage and Frequency Scaling (DVFS) to save power. In this paper, we discuss the basics of SRAM faliure mechanisms, fundamentals of write assist techniques, ARM® Artisan® Low Voltage Memory Compilers with the write assist feature and results from GLOBALFOUNDRIES 28nm-SLP memories.
June - 2012
- Enea Element®: Simplify Distributed Systems with Frameworks from Enea Element
Distributed systems range from simple multi-threaded applications to multi-slot chassis-based systems to networked clusters of servers. Topologies get more complex when these systems move into cloud-based environments, and more diverse when they involve machine-to-machine (or M2M) solutions. Providers of distributed system software solutions face a number of challenges in building, debugging and maintaining a set of connected applications. Managing these systems requires powerful modeling and a variety of management interfaces to meet a diverse set of needs. The services provided by a distributed system often require a high level of availability. The middleware frameworks that make up Enea Element address many of these challenges.
- Redefining RF and Microwave Instrumentation Through Open Software and Modular Hardware
National Instruments uses multicore processors, user-programmable FPGAs, the high-throughput PCI Express system bus in PXI, and LabVIEW graphical system design software to address the business and technology challenges of high-frequency test and measurement. Read the white paper.
May - 2012
- VPX for High-Performance Avionic Computers
Traditional high-performance computing platforms are limited by the connection bandwidth and latency between the multiple computing elements needed to achieve the performance targets. For the embedded market, the difficulty is compounded by the demanding environmental requirements. The VPX standard resolves this limitation with a large number of high-throughput point-to-point connections between the processing elements in a rugged mechanical structure.
- OpenVPX System Bandwidth: A comparison of 10Gb Ethernet Performance, Serial Rapid IO, and InfiniBand
This paper compares the bandwidth available to two common types of dataflow for systems based on the VITA 65 CEN16 central switched topology, using three different fabrics – Serial RapidIO (SRIO), 10 Gigabit Ethernet (10GbE), and Double Data Rate InfiniBand (DDR IB).
- Xilinx 7 Series FPGAs: The Logical Advantage
Configurable logic tiles are the fundamental building blocks of all programmable digital electronic systems. Ever since Xilinx invented the FPGA in the 1980s, configurable logic, in the form of look-up tables and registers, has been an essential component of digital electronics systems across all markets and applications. This white paper describes the features of the configurable logic block in the 28 nm Xilinx 7 series FPGAs, highlighting advantages over previous Xilinx FPGAs and the benefits that these changes bring to the digital design engineer.
February - 2012
- LTE-Advanced Signal Generation and Measurement Using SystemVue
LTE-Advanced is specified as part of Release 10 of the 3GPP specifications and is now approved for 4G IMT-Advanced. This application note introduces key LTE-Advanced techniques, as well as how to use the Agilent SystemVue W1918 LTE-Advanced library to generate various downlink (DL) orthogonal frequencydivision multiple access (OFDMA) and uplink (UL) clustered DFT-spread-OFDM (DFT-S-OFDM) signal sources with MIMO, and to measure closed-loop throughput.
This application note also introduces LTE-Advanced enhancements to the MIMO channel models, which are available as simulation model set called the W1715 SystemVue MIMO channel builder. This optional model set facilitates simulation-based MIMO over-the-air (OTA) testing using real, observed antenna patterns and standard MIMO fading models, and overcomes a key challenge for 8-layer MIMO system analysis and verification.
August - 2011
- Best Practice Development Processes for Medical Device FPGAs
For FPGA developers working on designs for medical devices, one approach to dealing with regulatory uncertainty is to borrow heavily from design assurance processes in other safety-critical industries, such as avionics, where standards are well established. These well-established standards mandate a development flow that is controlled, auditable and perhaps most important, specific to the requirements of hardware engineering. While following such a flow will not guarantee smooth sailing though every regulatory approval process for FPGA devices bound for medical applications, it is consistent with basic regulatory intent - to demonstrate to auditors that complex devices meet their requirements and perform well under all foreseeable conditions.
May - 2011
- Direct Power MOSFET Capacitance Measurement at 3000 V
Learn how to make power MOSFET capacitance measurements at up to 3000 V of DC bias.
- Common Pitfalls in PCI Express Design
PCI Express is a point-to-point communications interface. It is neither an evolved nor enhanced form of PCI or PCI-X, but, essentially, a high speed, low voltage, differential serial pathway for communication between two devices, although it uses the same programming model as its predecessors.
April - 2011
- Increasing Revenue Through Continuously Optimized Data Center Management
Most businesses are completely dependent on technology, and the impact of using non-optimized technology can be directly measured in their revenue. Why? Because as widespread dependence on technology has grown, the size and complexity of the technology’s environment has grown in a non-linear manner.
January - 2011
- Designing For Low Power
Power consumption is becoming an increasingly important variable when it comes to calculating OPEX and carbon footprint for telecom infrastructure projects.
November - 2010
- 10 Reasons to Customize A Processor Core
There are plenty of really good, proven processor cores on the market today. But if you have more than simple control tasks, perhaps you’ve considered using a processor that you can customize. We’ll give you 10 good reasons why you should consider customizing your core in your next SOC design.
- The What, Why, and How of Customizable Dataplane Processors (DPUs)
Designers have long understood how to use a single processor for the control functions in a SOC design. However, there are a lot of data-intensive functions that control processors cannot handle. That’s why designers design RTL blocks for these functions. However, RTL blocks take a long time to design and even longer to verify, and they are not programmable to handle multiple standard or designs.
- Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC
Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC [company]
- Cut DSP Development Time – Get High Performance From C, No Assembly Required
Cut DSP Development Time – Get High Performance From C, No Assembly Required [company]
- Get Your ASICs and SOCs Off the Bus!
Get Your ASICs and SOCs Off the Bus! [company]
- The Five Pitfalls of 4G Baseband SOC Design
The Five Pitfalls of 4G Baseband SOC Design [company]
October - 2010
- Silicon On Insulator (SOI) Implementation
Increased demand for high performance, low power and smaller area among microelectronic devices is continuously pushing the fabrication process to go beyond ultra-deep sub-micron (UDSM) technologies, leading to an alternative, Silicon On Insulator (SOI) process. The paper introduces SOI technology, talks about the design challenges associated with ASIC implementation with SOI for today’s complex designs and finally lists out implementation guidelines to overcome these challenges.