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As IP and IC designers and verification teams tackle increased complexity and expectations, reliability verification has become a necessary ingredient for success. Automotive, always-on mobile devices, IOT and other platforms require increasingly lower power envelopes and reduced device leakage while maintaining overall device performance. Foundries have also created new process nodes targeted for these applications. Having the ability to establish baseline checks for design and reliability requirements is critical to first pass success.
The upcoming IEEE 802.11ax High-Efficiency Wireless (HEW) standard promises to deliver four times greater data throughput per user. It relies on multiuser technologies to make better use of the available Wi-Fi channels and serve more devices in dense user environments. Explore this technology introduction white paper to learn about the new applications of 802.11ax, the key technical innovations to the standard, and its test and measurement challenges.
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This paper introduces an acceleration-ready UVM framework and explains why it is needed, how to create it, and what its benefits are. By following the principles presented here, users will be able to write block-level UVM environments that can be reused directly in emulation. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain over pure simulation and significantly reducing testbench development time for emulation.
When debugging software on an emulator with a probe, something is always waiting. When the software developer is looking at memory, variables, and source code the emulator is occupied. With Codelink, most the waiting is eliminated as the developer interacts with a virtual target which is run on the same host as the debugger, eliminating the delays you get with a probe debugger. Because the virtual target is processing much less data than the original emulation, it can run faster â more than 10 times faster. This means 10 times less waiting for the developer. Download the paper to learn more.
Manage performance, database size and accuracy before, during and after design. Download your free whitepaper to learn how the new Calibre nmLVS boxing capabilities help manage these trade-offs by allowing:
Designers need to start planning for PCI Express 4.0 integration now, because decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper
Growing internet traffic impacts how cloud and carrier data center operators design compute and data networking architectures. To meet demands for scale-out servers and networks, designers
This white paper explores the issues facing SoC designers as they address SoC complexity and time-to-market challenges. High-quality IP alone is not enough with todayâs SoC complexity.
This white paper digs into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the specification. USB 3.1 introduces a 10 Gbps signaling rate in addition to other features.
Read about a method to determine if the electrical characteristics of any given AFE are adequate for the targeted application. Also, learn about a tool to explore tradeoffs between
The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Key challenges in the design of these circuits include block-level characterization and full-circuit verification. This paper highlights these verification challenges by discussing the results of a 2.2 GHz PLL LC-VCO, a 12-bit pipeline ADC, and an ultra-wideband transceiver.
This paper describes a new circuit validation and characterization flow that enables users to easily set up, run, record pass/fail, and analyze very complex tests. The validation and characterization flow was standardized across the design team, leveraging knowledge and computing resources and significantly improving design productivity.
This paper describes how AFS Transient Noise analysis enables circuit designers to efficiently perform SPICE-accurate device noise analysis on complex non-periodic analog/RF blocks. This capability enables designers to measure and optimize device noise analysis on complex blocks such as ADCs, frac-N PLLs, and int-N PLLs which would not otherwise have been possible without silicon iterations.
Automotive electronics play a critical role in today's automotive safety systems. While standards like ISO 26262 provide a framework for robust and reliable design and verification
Chip-package co-design is important for several reasons. Designing a large high power die, e.g. a System-on-Chip (SoC) without considering how to get the heat out is likely to lead
Data center power load (and therefore heat dissipation) footprints continue to rise in response to growing demand for information storage and transfer. Cooling constitutes a major cost in the operation of a data center which has led to increased focus on minimizing energy use in data centers.
A natural focus when designing electronics products are, well the electronics. The electronics itself however, needs to work within some kind of enclosure, and must be designed with the enclosure in mind. Cooling is a system issue, which is why we advocate a top-down approach, starting at the enclosure level.
Many aspects of a PCBâs performance are determined during detailed design. Thermal issues with the PCB design are largely âlocked inâ during the component (i.e. chip package)
Recently, physics-based reliability prediction has related electronic assembly failure rates to the rate and magnitude of temperature change over an operational cycle, both of which are influenced by steady-state operating temperature. Whether the intention is to increase reliability, or improve performance, accurate prediction of component temperatures helps meet design goals.
ASIC and & FPGAs have many false paths that implementation tools attempt to optimize to make timing goals. Adding false path constraints frees up the synthesis tool to work only on necessary paths. Blue Pearl automates false path generation that can be run after design changes
This paper introduces a novel technique for Intellectual Property (IP) and FPGA clock domain crossing (CDC) analysis using Blue Pearlâs User Grey Cellâ¢ methodology rather than the traditional Black Box methodology.
Packet processor design teams face increasingly difficult challenges as they seek to provide their network equipment manufacturers with state-of-the-art devices. The interrelated system-level trade-offs include performance, pin count, and area, and are all ultimately limited by power consumption considerations. To successfully compete, network chip vendors must consider end-to-end solutions for system architects and developers. In turn, as OEMs introduce multi-terabit systems, they must aggregate multiple 100 Gbps ports on each line card or risk falling behind the performance curve.
An FPGA Approach to Implementing Time-Critical Functions in Multi-Sensor Mobile Designs.
Taking full advantage of the performances of the 7 Series FPGAs can be done by using the high speed memory controller from Barco Silex, which has been reworked to achieve the highest frequency and efficiency.
Write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. One of the key reasons to push the SRAM Vmin lower is to enable efficient Dynamic Voltage and Frequency Scaling (DVFS) to save power. In this paper, we discuss the basics of SRAM faliure mechanisms, fundamentals of write assist techniques, ARMÂ® ArtisanÂ® Low Voltage Memory Compilers with the write assist feature and results from GLOBALFOUNDRIES 28nm-SLP memories.