October - 2009

• Website
  Title
  
  
• Chip Design
  Evolving the Coverage-driven Verification Flow

  Verification methodology has undergone dramatic changes over the past decade. The realization that larger and more-complex designs required more and more verification effort, coupled with shrinking schedules, spawned new languages specifically tailored for verification and tools intended to make the verification process more predictable and efficient.
• Low Power Systems
  Power Consumption at 40 and 45 nm

  At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection.
• Embedded Processing & DSP
  Accurately Analyzing Power in a Simulink Software Model-Based Design Flow

  Frequency, run time, and area utilizations are widely used as benchmarking metrics to gauge quality of results (QoR) for FPGA designs and tool performance.
• Chip Design
  Capabilities to Maximize Productivity for FPGA Debug and Verification

  Whether your task is to verify the functional correctness of a design, ensure adequate timing performance, or to quickly bring up a hardware platform in the lab environment, efficient verification and debug typically requires evaluating the design from multiple perspectives—ranging from high-level functional characteristics to low-level performance details—each at different phases of the design flow.

June - 2009

• Website
  Title
  
  
• Chip Design
  Synopsys White Paper: Understanding the real cost of prototyping hardware

  This white paper provides an in depth look at significant factors to consider when choosing to develop or purchase prototyping hardware. Costs, development time, and effort are considered in detail as well as other factors such as Bill-of-materials cost, manufacturing time, and test yield. The paper also provides information on how to request a “Cost Comparison Spreadsheet” which will allow you to explore the various options and make an informed decision for your particular situation.

April - 2009

• Website
  Title
  
  
• Chip Design
  The PSP Model in RF CMOS Design

  This white paper explains the technology behind Penn State Philips (PSP) transistor models and how they relate to actual device behavior.