Synopsys, Inc.

DesignWare IP for PCI Express PHY

The PCI® PHY includes all of the required logical and physical design files needed for integration in a System-on-Chip (SOC) design. Industry standard PIPE interface and validated compatibility with the DesignWare® PCIe Endpoint Controller enable easy integration of the PCIe PHY into a variety of applications, ranging from server and desktop systems to mobile devices.

The PCIe PHY integrates high-speed mixed-signal custom CMOS circuitry compliant with the PCI Express® base specification and the PIPE interface standard. While extremely low in power consumption and area requirements,
Synopsys’ PCIe PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity.


  • Supports a wide range of configurations including 1.0v & 1.2v core supplies and 2.5v & 3.3v I/O supplies
  • Supports a wide range of PCIe bus widths (up to x8 support)
  • Fully compliant with PCI Express 1.0a and 1.0a Errata and PIPE interface to ensure interoperability and ease of integration with higher protocol levels


  • Supports all power-down states for highly efficient operation
  • Full support for beaconing, receiver detection and electrical idle
  • Reliable link operation across channel manufacturing operation (BER<10-18)


Available now.

Contact Information

Synopsys, Inc.

700 E. Middlefield Road
Mountain View, CA, 94043

tele: 650.584.5000

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