The Synopsys DesignWare® USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution.
DesignWare USB 2.0 nano PHY is designed for low power mobile and consumer applications such as next generation
handheld game machines, feature rich smart phones, digital cameras and portable audio/video players. The DesignWare USB 2.0 nanoPHY IP delivers approximately half the power and die area, compared to other solutions, for longer battery life and lower silicon cost. Designed for high yield, the DesignWare USB 2.0 nanoPHY implements
architectural features that make it less sensitive to variations in foundry process, device models, package and board parasitics. The DesignWare USB 2.0 nanoPHY builds on years of success with Synopsys. silicon-proven USB 2.0 PHY IP product line, which has been ported to over two dozen process node and configuration combinations.
When combined with the DesignWare Hi-Speed or On-The-Go (OTG) digital controllers and verification IP, the DesignWare USB 2.0 nanoPHY delivers a complete, low power and small die area solution for Hi-Speed and OTG enabled system-on-chip (SoC) designs.
- Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
- Low power: 65-100mW (during HS packet transmission)*
- Small area: ~ 0.6mm2 *
- High Yield – Architecture designed to improve key operating margins by having less sensitivity to variations due to foundry process, chip and board parasitics, and process device model variations
- Low pin count
* Actual results dependent on specific foundry process.