Famous Graphics Chips: NEC µPD7220 Graphics Display Controller

The first in a series about the graphics chips, controllers, and processors that have changed the course of the computer graphics industry.

In 1982, NEC changed the landscape of the emerging computer graphics market just as the PC was being introduced, altering a market that had been specialized and expensive. NEC Information Systems, the U.S. arm of the Nippon Electric Company (now NEC), introduced the µPD7220 Graphics Display Controller (GDC). The project was started in 1979 with a paper published in February 1981 at the IEEE International Solid State Circuit Conference.

Prior to the introduction of the GDC, PC graphics display systems came in two classes: high-end CAD systems hung on big IBM and DEC mainframes and low-end microcomputer systems based on the fledgling Intel 4004 CPU, a precursor of the PC.

Very Large-Scale Integration (VLSI) technology was just getting rolling, and devices with astounding numbers of transistors, 30,000 to 40,000, were being built with the precursor of complementary metal-oxide semiconductor (CMOS), negative metal-oxide semiconductor (NMOS). CMOS was expensive and had larger feature sizes. An NMOS chip could have gates as small as 5-micron. But they paid for that with power dissipation challenges. The µPD7220, running on 5 v, drew 1.5 W and used a 40-pin ceramic package.

Figure 1: NEC’s µPD7220 was the first integrated graphics controller chip (Drahtlos, Wikipedia)

The chip incorporated all the cathode ray tube (CRT) control functions (known as the cathode ray tube controller or CRTC) as well as graphics primitives for arcs, lines, circles, and special characters. Processor software overhead was minimized by the GDC’s sophisticated instruction set, graphics figure drawing, and DMA transfer capabilities. It supported a light pen and could drive up to four megabits of bit-mapped graphics memory, which was quite a lot for the time.

Figure 2: Layout of the µPD7220—notice the RAM areas.

Prior to the µPD7220 every graphics device had its own drawing primitives library, with IBM’s 2250 (1974), and Tektronix’s 4010 (1972) being the most popular. The µPD7220 established an easy to use, low-level set of instructions that application developers could easily embed in their programs and thereby speed up drawing time.

Achieving Control of the GDC
Control of the GDC by the system microprocessor was achieved through an 8-bit bidirectional interface, which also provided access to the first-in, first-out (FIFO) buffer. The command processor then interpreted the contents of the FIFO. The command bytes were decoded and the succeeding parameters distributed to their proper destinations within the GDC. The command processor would yield to the bus interface when both accessed the FIFO simultaneously.

In addition, the GDC had direct memory access (DMA) control circuitry that could coordinate data transfers over the microprocessor interface when using an external DMA controller.

There were 16-byte random access memory (RAM) storing parameters that were used repetitively during the display and drawing processes. In character mode, the RAM held four sets of partitioned display area parameters; in graphics mode, the drawing pattern and graphics character took the place of two of the sets of parameters.

Based on the clock input, built-in sync logic would generate raster timing signals for almost any interlaced, noninterlaced, or “repeat field” interlaced video format. The generator was programmed during the idle period following a reset. In video sync slave mode, it coordinated timing between multiple GDCs.

It was a great demonstration of VLSI, incorporating dozens of functions in one chip.

Figure 3: Block diagram of µPD7220

The chip’s memory timing circuitry provided two memory cycle types: a two-clock period refresh cycle and the read-modify-write (RMW) cycle which took four clock periods.

The chip also had programmable zoom capability. The display area entries in the parameter RAM, combined with the zoom and pan controller, determined when to advance to the next memory address for display refresh and when to go on to the next display area. A horizontal zoom was cleverly produced by slowing down the display refresh rate while maintaining the video sync rates. Vertical zoom was accomplished by repeatedly accessing each line a number of times equal to the horizontal repeat. Once the line count for a display area was exhausted, the controller accessed the starting address and line count of the next display area from the parameter RAM.

A Major Breakthrough
The graphics heart of the device was its drawing processor, which contained the logic necessary to calculate the addresses and positions of the pixels of the various graphics figures. Given a starting point and the appropriate drawing parameters, the drawing controller didn’t need any assistance to complete the figure drawing—a major breakthrough for an integrated controller of the time.

The display memory controller’s tasks however, were numerous. Its primary purpose was to multiplex the address and data information in and out of the display memory. It also contained the 16-bit logic unit used to modify the display memory contents during RMW cycles, the character mode line counter, and the refresh counter for dynamic RAMs. The memory controller apportioned the video field time between the various types of cycles.

Raster graphics was just coming into its own, and in the high-end graphics display market, the tubes were vector writers. They were very accurate, and one could actually make measurements from the screen. Using a photo-sensitive light pen made it possible to manipulate lines and other graphics objects. The pen would detect the light from the screen and through x-y timing signals know where the pen was looking. The µPD7220 incorporated those features, too.

Only if two rising edges on the light pen input occurred at the same point during successive video fields were the pulses accepted as a valid light pen detection. A status bit indicated to the system microprocessor that the light pen register contained a valid address.

The chip quickly became popular and was the basis for several “dumb” terminals and a few graphics terminals (a “dumb” terminal being one that couldn’t be programmed and just displayed images and/or text). The controller could support 1024 × 1024 resolutions with four planes of color, so some systems employed multiple 7220s to get more color depth. In June 1983, Intel brought out the 82720, a clone of the µPD7220.

The µPD7220 was produced until 1987 when it was replaced by a newer, faster version, the µPD72120. Seeing its success and the emerging market for computer graphics, Hitachi and TI also introduced graphics processors a few years later.

You can find out more about this chip and its successors here.

In the next article we’ll delve into the successor to the µPD7220, the very popular Hitachi ACTRC HD63484, which eclipsed the pioneering 7220 in unit shipments, only to be superseded, too. Moore’s law and the computer graphics industry are unrelenting.

Dr. Jon Peddie is one of the pioneers of the graphics industry and formed Jon Peddie Research (JPR) to provide customer intimate consulting and market forecasting services where he explores the developments in computer graphics technology to advance economic inclusion and improve resource efficiency.

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