SAN JOSE, Calif., February 5, 2007 – CoWare, Inc., the leading supplier of platform-driven electronic system-level (ESL) design software and services, announced a new release of CoWare Processor Designer that provides increased support for next-generation Very Long Instruction Word (VLIW) digital signal processors (DSPs). The new CoWare Processor Designer enables users to explore a large design space to ensure that the targeted processing power is achieved and the interconnect infrastructure is available to feed data into the processor at an acceptable rate. The latter can only be done in the platform context. Only CoWare has the combined offering of processor development and platform design to provide the full solution. Without this capability, architecture exploration can take up to several months. Now, with CoWare Processor Designer, it can be done in a matter of hours.
VLIW DSP architectures have proven to be an optimal target for today’s C compiler technology. VLIW DSP architectures do not require designs to sacrifice software development productivity for the very high-performance processing needed for the next-generation high-end video, multimedia and wireless devices. Companies developing high-end video processing devices that implement the next generation H.264 or VC1 video standards and companies
developing wireless baseband processing devices targeting the next generation WiMAX or LTE
(next-generation W-CDMA) wireless standards can benefit the most from the new capabilities in Processor Designer. With the software programmability available through the Processor Designer flow, users can make adjustments for late changes in the standards and provide devices that can be programmed for different standards. This can be done while maintaining the performance of custom hardware.
If redundant parallel data paths are included, they make the design too expensive. Very specific customization of every application is required to be cost effective. The new enhancements to the LISA language, which are now available through CoWare Processor Designer, enable users to parameterize the processor architecture with the number of parallel data paths (VLIW slots) to determine the optimal number of slots for a specific application and then customize each slot individually. The new Processor Designer fully automates the exploration of the number of parallel data paths by generating software development tools such as assembler, linker, simulator, and a highly-optimizing C complier for software performance measurement, as well as RTL code generation for hardware cost estimation. The result is that the user can script the exploration of various architectures with different data paths in a matter of hours rather than months.
“A start-up company still in â€˜stealth’ mode made use of the new VLIW support in CoWare Processor Designer to model its new processor architecture,” said Dr. Andrea Kroll, product marketing director, CoWare. “According to the company’s CEO, Processor Designer enabled his team to demonstrate its new architecture to investors and new customers early, before the silicon was available, specifically because the modeling could be done very quickly.” Added Kroll, “Similarly, CoWare Processor Designer tools enabled a large U.S.-based semiconductor company to provide its customers with early access to its next-generation architecture. This gave the company a unique ‘go-to-market’ advantage because its customers could provide very early feedback.”
Continued Kroll, “CoWare Processor Designer is unique because it can generate, from one specification, all the software development tools and the RTL for processor architects, software developers and hardware designers. Other tools require multiple, independent specifications to generate the individual solutions that might not be consistent. With
CoWare’s one specification approach, there is a real time savings for the user.”
New CoWare Processor Designer Provides Much Faster DSP Architecture Exploration
New features in the most recent release of Processor Designer contribute to the overall benefit of faster architecture exploration:
- Full C compiler support for the new VLIW language extensions to enable quick exploration on the number of parallel instructions suitable for a specific application or application space
- Efficient RTL generation from one specification, which enables quick cost analysis of the VLIW architecture
- Unified debugging environment for standalone and system-level debugging to enable advanced debugging for the software application jointly with the processor and the platform hardware, which improves processor design and software development productivity