Synopsys and jNet ThingX Optimize JavaCard OS for Synopsys’ ARC SEM Security Processors

Synopsys, Inc. and jNet ThingX announced that jNet ThingX’s JavaCard/GlobalPlatform OS has been ported and optimized for Synopsys’ DesignWare ARC SEM security processors, creating a highly secure HW/SW platform for embedded applications. The JavaCard v3.0.4 and GlobalPlatform v2.2.1 specifications support Common Criteria (CC) certification up to Evaluation Assurance Level (EAL) 5+, a rating typically associated with smartcards and devices with similarly stringent security requirements.

Synopsys’ ARC SEM processors with SecureShield technology enable designers to separate secure and non-secure functions as part of a Trusted Execution Environment (TEE) and protect devices from evolving security threats, including side-channel attacks. By running JavaCard OS on ARC SEM processors, developers can create more secure SoCs for a broad spectrum of low-power mobile, industrial and IoT applications, including near-field communication (NFC) payment, government documents/IDs, smart cards, smart meters and over-the-air provisioning using embedded Universal Integrated Circuit Card (eUICC) and embedded SIM (eSIM).

“With the requirements for secure chips expanding beyond traditional smartcards and into a wide range of connected devices, the combination of the ARC SEM security processor with our JavaCard technology creates a compelling platform for security-critical applications,” said Mikhail Friedland, CEO at jNet ThingX Corporation.

jNet ThingX develops the JavaCard OS, including GlobalPlatform support, for implementation in security-critical embedded applications such as payment cards, government ID and eUICC/eSIM. The JavaCard OS includes JavaCard Virtual Machine (JCVM), JavaCard Runtime Environment (JCRE), JavaCard API class libraries, Crypto library and GlobalPlatform support. Developing in Java is associated with fewer software defects, lower software maintenance costs and a reduction in time to market.

Synopsys’ DesignWare ARC SEM110 and SEM120D security processors are optimized for area and power efficiency while integrating anti-tamper features, making them ideally suited for a wide range of low-power embedded security applications. The ARC SEM processor cores provide side-channel resistance through timing and power randomization, and uniform instruction timing capabilities that obfuscate critical operations from potential hackers. The available SecureShield runtime libraries simplify development of a TEE, ensuring that sensitive data is stored, processed and protected in an isolated environment. In addition, the ARC CryptoPack option accelerates common cryptographic algorithms such as AES, SHA-256, RSA and ECC by adding custom instructions to the ARC SEM processor.

Contact Information

Synopsys, Inc.

700 E. Middlefield Road
Mountain View, CA, 94043

tele: 650.584.5000

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