Ethernet Applications Leveraging FPGAs

Helping system architects create more power-efficient Ethernet interfaces in smaller form factors.

The growing use of Ethernet connectivity and increasing pressure to reduce costs are two networking mega trends that continue unimpeded. Ethernet ports have continually increased in performance and are found on a wider range of products, thanks to expanding networks and the Internet of Things (IoT). Network operators are under increased pressure to significantly reduce capital expenditures (CAPEX/OPEX) while simultaneously delivering faster performance to support consumer applications like 4K video and ubiquitous cloud connectivity. To assist architects in delivering on these market demands requires a redefined category of mid-range FPGAs, a family that is purpose-built and specifically architected to reduce cost, with lower power, and providing key Ethernet connectivity for a wide range of communications applications.

These new market realities are creating major challenges for vendors who design Ethernet-based communications equipment. The sweet spot for Ethernet continues to be the 1 Gbps to 10 Gbps line rates, and numerous access and gateways are being designed to add compute capabilities at the edge of the network. Delivering these solutions at a lower cost requires a system view of the application. To cut costs, lower power solutions could be leveraged to eliminate fans or heat sinks, or, instead of creating a dedicated bridging product, that functionality could be implemented in an SFP-type form factor, cutting down the size of the PCB and overall form factor. These solutions require the appropriate Ethernet connectivity with lower power in a cost-optimized, small form factor package. System architects now have solutions that can help them create more power-efficient Ethernet interfaces in smaller form factors, all provided in a cost-optimized, flexible FPGA.

Small Form Factors Enable Unique Ethernet Solutions
The demand for lower CAPEX/OPEX is leading developers to squeeze communications products into much smaller spaces, and FPGAs are often a key design component in Ethernet applications. Today, there exists an optimized mid-range density FPGA that combines adequate interface performance with the lowest power and smallest possible sizes. Many low-density FPGAs have small packages, but lack adequate performance interfaces (such as 10 Gbps transceivers), while most mid-range architectures lack smaller packages and consume significant power. Crucial features that must be incorporated into smaller physical packages include 10 Gbps transceivers, a generous amount of embedded memory, numerous 3.3 V I/Os, and interfaces to newer memory standards. The availability of FPGAs that deliver these capabilities with a power-optimized architecture for mid-range densities is a key enabler for the coming generation of small-footprint solutions.

Figure 1: Smallest Size, Lower Power, Mid-range Density FPGAs with Support for 10 Gbps Ethernet

Figure 1: Smallest Size, Lower Power, Mid-range Density FPGAs with Support for 10 Gbps Ethernet

The requirement for smaller footprints is very clear for optical modules or SFP-type modules. Many Ethernet communication products have SFP cages or similar housings that can accept transceiver interfaces and normally run at speeds from 1 Gbps to 10 Gbps. Products that can implement functions in these modules enable additional system-level flexibility and lower costs.

For example, a gateway that supports 10 Gbps Ethernet may not always require synchronous network timing, such as SyncE or IEEE 1588. If an SFP cage is designed into the product, then a specifically designed SFP that supports SyncE could be used instead. This frees a system architect from having to implement the function as part of the gateway, and decreases the overall cost for customers who do not require the synchronous network timing. Users who need the SyncE network timing can simply plug in the specifically-designed SFP module. Although many low-end FPGAs are small enough to fit the size requirements for this application, the necessary resources are beyond the capabilities of low-end FPGAs. A typical mid-range FPGA can support 10 Gbps Ethernet, but their power and size do not work for an SFP type module. However, solutions now available include, for example, the PolarFire FPGA family from Microsemi, which provides two densities that are available in packages only 11 mm wide. These devices are optimized for cost and low power consumption, with have Ethernet capabilities up to 10 Gbps. These PolarFire FPGAs are class-leading in the smallest size.

Power-efficient Gigabit Ethernet interfaces are driving changes in system architectures. Many communication product developers are using Gigabit Ethernet for an increasing number of connections. No longer only for data payloads, these links are becoming ubiquitous for control, management, status, and more. Often, these growing numbers of Gigabit Ethernet links will be aggregated or multiplexed to a 10G Ethernet link. Traditional mid-range FPGAs can support these 1 Gbps to 10 Gbps speeds, but require transceivers to implement both the 1G serial gigabit media-independent interface (SGMII) and 10G 10BASE-R or 10BASE-KR. Ideally, a device would have generic I/O pins that could support SGMII, as Figure 2 shows.

Figure 2: FPGA Implementing serial gigabit media-independent interface (SGMII in GPIOs

Figure 2: FPGA Implementing serial gigabit media-independent interface (SGMII) in GPIOs

Traditional mid-range FPGAs do not have this feature and so must rely on transceivers. These transceiver interfaces are precious and frequently scarce, unless very expensive, higher density FPGA fabrics are used. The very large FPGA fabric is often not required, but designers are forced to choose these devices because they require additional transceivers. In addition, these larger devices dictate that larger package form factors are required. These existing solutions increase both power consumption and cost in opposition to OPEX demands.

The new PolarFire FPGAs offer power-optimized mid-range densities and address the requirement for numerous GigE and 10 GigE links. The family spans from 100K LEs to 500K LEs, and these devices feature 8 to 24 12.7 Gbps transceivers that can support Ethernet from 1 Gbps to 10 Gbps. What differentiates the PolarFire FPGAs is that they have incorporated a clock and data recovery (CDR) circuit into high-speed LVDS I/Os that can run beyond 1.25 Gbps. This allows the device to support SGMII interfaces on several select GPIO pins. Designs that require a mix of Gigabit and 10 Gigabit Ethernet can now select between using transceivers and GPIO pins with CDRs to support their interfaces, as described in the following table.

Table 1: PolarFire FPGA Family with CDRs in GPIOs

Table 1: PolarFire FPGA Family with CDRs in GPIOs

Engineers no longer have to select larger package devices for the additional transceivers. PolarFire FPGAs allow smaller packages to be chosen. These GPIO CDRs also consume less power than a transceiver, which reduces the overall power consumption for applications using multiple GigE links and offers a valuable strategy for reducing CAPEX/OPEX.

Dominating Power Consumption
Communications applications have also often been a driver for lower power. FPGAs often consume a sizeable allocation of the power budget. The two largest drivers of power for FPGAs are static power and transceiver power. PolarFire FPGAs shine in both these categories. For an SRAM FPGA, static power can generate up to half the total power consumption. As these devices have moved to advanced manufacturing nodes, the static power has become a dominant component in the total power consumption. Conversely, PolarFire FPGAs are built on a non-volatile process. This results in the devices consuming approximately 1/10th the static power of an equivalent SRAM device. The other power gobblers are the transceivers. Mid-range density SRAM FPGAs typically consume 160 mW–200 mW of power for each 10 Gbps interface. The PolarFire FPGAs typically consume only 90 mW for the same function. In addition, recall that this device can also implement SGMII in GPIOs. When this interface is utilized, the power consumption for each 1 Gbps interface is typically less than 30 mW. By consuming the lowest static power and with the most power efficient 1 Gbps and 10 Gbps Ethernet interfaces, PolarFire FPGAs deliver up to 5 percent lower power than similar mid-range density SRAM FPGAs.

The driving trends of Ethernet-based communication applications necessitate that engineers look for new solutions. Mid-range-density FPGAs are now available to optimally address 1 Gbps and 10 Gbps-Ethernet based applications. Whether these are access points, SFPs, gateways, routers, or other devices, designers are no longer forced to sacrifice cost and power efficiency in order to achieve the necessary requirements. The PolarFire mid-range FPGAs offer lower power, smaller size form factors, and optimized Ethernet interfaces to meet the latest demands of the Ethernet communications market.

Ted-Marena-Microsemi_webTed Marena is the director of FPGA/SOC marketing at Microsemi. He has over 20 years’ experience in FPGAs. Previously Marena has held roles in design engineering, technical sales/support, business development, product and strategic marketing. He was awarded Innovator of the Year in February 2014 when he worked for Lattice Semiconductor. Marena has defined, created and executed unique marketing platform solutions for vertical markets including consumer, wireless small cells, industrial, cameras, displays and automotive applications. Marena holds a Bachelor of Science in electrical engineering Magna Cum Laude from the University of Connecticut and a MBA from Bentley University’s Elkin B. McCallum Graduate School of Business.

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