This paper compares the bandwidth available to two common types of dataflow for systems based on the VITA 65 CEN16 central switched topology, using three different fabrics – Serial RapidIO (SRIO), 10 Gigabit Ethernet (10GbE), and Double Data Rate InfiniBand (DDR IB).
Xilinx has chosen 28 nm high-metal gate (HKMG) high performance, low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. This white paper describes the challenges the semiconductor industry faces in addressing market requirements and describes how these can be solved with the right 28 nm process technology. The breakthrough combination of a high performance, low-power process with architectural innovations makes new 28 nm FPGAs well suited for power sensitive applications, bandwidth-intensive, and ultra-high end applications.
Key strategic design decisions made early in the development cycle often have far-reaching impact on the overall results achieved with the final design. Xilinx offers many product solutions with single and multiple on-chip processing elements, such as multiple MicroBlaze™ processors or ARM® Cortex™-A9 processors, DMA engines, communications, video, and DSP IP. Evaluation Kits and Targeted Design Platforms are available to serve both as sample system designs and as advanced FPGA development platforms for the underlying FPGA selection.
Configurable logic tiles are the fundamental building blocks of all programmable digital electronic systems. Ever since Xilinx invented the FPGA in the 1980s, configurable logic, in the form of look-up tables and registers, has been an essential component of digital electronics systems across all markets and applications. This white paper describes the features of the configurable logic block in the 28 nm Xilinx 7 series FPGAs, highlighting advantages over previous Xilinx FPGAs and the benefits that these changes bring to the digital design engineer.
This white paper describes several aspects of power related to the Xilinx® 28 nm 7 series FPGAs, including the TSMC 28 nm high-k metal gate (HKMG), high performance, low power (28 nm HPL or 28 HPL) process choice. The power benefits afforded by the 28 HPL process and its usefulness across Xilinx's full product offerings is described as well as the architectural innovations and features for power reduction across the dimensions of static power, dynamic power, and I/O power.
Conceived and designed for high-volume markets, Artix-7 FPGAs deliver the lowest power consumption and lowest cost in the 7 series. The family shares the same building blocks as the Kintex-7 and Virtex-7 FPGA architecture on the same 28 nm High Performance, Low Power (HPL) process, but transistor-level design choices enable the Artix-7 family to offer much lower power consumption while still meeting the performance needs of the target applications.
LTE-Advanced is specified as part of Release 10 of the 3GPP specifications and is now approved for 4G IMT-Advanced. This application note introduces key LTE-Advanced techniques, as well as how to use the Agilent SystemVue W1918 LTE-Advanced library to generate various downlink (DL) orthogonal frequencydivision multiple access (OFDMA) and uplink (UL) clustered DFT-spread-OFDM (DFT-S-OFDM) signal sources with MIMO, and to measure closed-loop throughput.
This application note also introduces LTE-Advanced enhancements to the MIMO channel models, which are available as simulation model set called the W1715 SystemVue MIMO channel builder. This optional model set facilitates simulation-based MIMO over-the-air (OTA) testing using real, observed antenna patterns and standard MIMO fading models, and overcomes a key challenge for 8-layer MIMO system analysis and verification.
