ASIC Prototyping Trends Extend FPGA Growth
Changing market conditions and designer needs point to growth in hardware prototypes and some software models.
One of the semiconductor industry bright spots in 2008 is the Programmable Logic Device (PLD) market, according to research firm iSuppli. A recent iSupply report reveals that the PLD market will enjoy healthy growth in 2008 with revenue increasing by 7.6 percent. According to iSuppli sources, the PLD market is led by U.S. supplier Xilinx Inc. (www. Xilinx.com), with expected 6.5 percent growth in 2008.
Growth in the overall semiconductor chip market, however, is expected to decrease by 2 percent this year, due mainly to poor sales of memory integrated circuits (ICs). One reason for the slow down in the overall chip market is the continuing decline in new applicationspecific- integrated-circuit (ASIC) projects. But that’s only part of the story. Though ASIC project starts are declining, the complexity of most ASIC designs is steadily increasing. This means that more time and money must be spent to verify the design of increasingly complex ASIC. What does the complexity of ASICs have to do with PLDs, especially field programmable gate arrays (FPGAs) – which make up the largest portion of the PLD market?
“It’s far more efficient to emulate a chip design in hardware than to simulate it in software,” explains Bruce Fienberg, Senior Group Communications Manager at Xilinx. “ASIC designers, which in many cases include designers of application-specific-standard-products (ASSPs), increasingly turn to FPGAs in order to run their designs,” notes Bruce. Another plus for FPGAs is the increasing sophistication of these devices. FPGAs now have greater circuit density, faster performance and other capabilities than in previous years. Such device improvements mean that fewer FPGAs are needed for prototyping an ASIC design relative to previous years.
The complexity of ASIC design increases with every process generation. Today’s leading edge chips are manufactured at the 45 nm process node, with some memory chips using 40nm technology. Even at the still popular higher process nodes of 180 and 130 nm, however, complexity is increasing as designers attempt to squeeze in more feature sets. Meanwhile, both the power budget and chip size are shrinking. This growing complexity—combined with the shift to time-sensitive consumer product markets—has led to an increase in the use of prototypes to verify these chips prior to production.
What do users really seek in prototyping tools? The report that follows contains the summary and analysis of a survey conducted with over 270 qualified respondents in the application-specific-integrated-circuit (ASIC) and related markets. Although the results track well with similar surveys in this space, the details present some surprising implications.
Most responders listed the communication market as their primary product area, followed closely by the consumer, computer, and other Most responders listed the communication market as their primary product area, followed closely by the consumer, computer, and other markets (see Figure 1). The most prevalent “other” markets were
Fig 1: Application Markets
In the category of communications, most respondents listed wireless handsets and wireless and wired networking as their chief application areas. These were followed closely by wireless base-station design, telephony/voice-over-IP (VoIP), and wireless metro-area networks (MANs). A small percent listed research, remote controllers, CDMA networks, fixed networks, telemetry, and military as other areas of focus within the communications category.
In the consumer market, most respondents listed multimedia designs involving both video and audio subsystems as their primary area for developing ASIC prototypes. Multimedia design concerns will be reflected proportionately in other parts of this survey (i.e., processor types, interfaces, etc.). Interestingly, several designers listed games as their chief concern, which is a trend that we’ll watch in future surveys.
Computer design issues were most closely tied to peripherals like storage, printers, and the like. PC and workstation systems came next with “other” including prototyping systems, servers, data-acquisition modules, and instrumentation and software/firmware design issues.
Fig 2: Job Functions
Most respondents identified themselves as ASIC or applicationspecific- standard-product (ASSP) designers (see Figure 2). These categories were followed by engineering management, corporate management, verification engineers, system architects, and software designers. In addition, a small percentage of users listed their functions as application engineers, business development, academia, and sales/marketing.
ASIC/ASSP/SoC Design Details
When asked to describe their current ASIC/ASSP/system-on-a-chip (SoC) design, over half of the respondents indicated a design size of less than 5M gates. The majority were below 2M gates. In terms of memory, most designers focus on SRAM memory, suggesting the strength of on-chip memory prototyping. Still, DDR and Flash memory each account for about 22% of memory usages.
Embedded-processor usage is led by the MIPS processor, which matches up with the responders’ application markets. ARM, Tensilica, and Intel each comprised roughly 16% of the remaining usage. Other processors used for ASIC prototyping ran the gamut from microcontrollers like the 8051, and Xilinx’s MicroBlaze to proprietary cores. A large number of digital-signal-processor (DSP) cores also were cited. They included Ceva Teak Lite, Texas Instruments, and in-house multimedia DSPs.
To the question concerning the types of external interfaces used for ASIC prototyping projects, the top three buses were PCI, USB, and Ethernet. SPI, SATA, XAUI, and HDMI finish up the lower quadrant. Though not listed in the survey, questions have arisen about the use of the PC-104 bus. Several experts feel that PCI Express represents the path forward for PC-104. This projected growth will be the subject of a future survey.
The majority of users listed Serial RapidIO (sRIO) as the main external bus of choice under the “other interface” category. This isn’t a surprise, as the sRIO interface is commonly used to connect multiprocessor designs (especially for DSPs). This finding tracks well with the use of DSPs highlighted in the “processor” usage category cited earlier. Other interfaces include the following:
A little over half of the respondents indicated that their previous design project required no respin. Of those acknowledging that respins were necessary, 50% stated that only one respin was needed. About half as many reported that two respins were required and slightly less than 10% admitted to three respins.
The main reason for chip respins was the presence of logical and functional errors (see Figure 3). This finding tracks well with other recent studies, which indicate that more than 60% of respun ASICs fail due to logical/functional errors (not because of timing or power issues). Clearly, functional verification is now the most critical phase of the chip development cycle.
Fig 3: Reasons for Chip Respins
When asked what type of verification was used for a current project and planned for future work, the largest groups of respondents selected Mentor’s ModelSim/Questa. This was followed by Cadence NC Simulator and Synopsys VCS (see Figure 4).
Fig 4: Verification Environments
Other software simulation environments consisted of IBM tools, Altera’s QuartusII, Xilinx’s ISE, homegrown systems and others.
In terms of emulators, most users listed Cadence systems followed by Mentor and Eve. An interesting side note is that only Eve emulators saw a planned increase for future projects. The formal-verification favorite was Formality, which was followed distantly by OneSpin, Real Intent, and Certess. System Verilog led the way in assertionbased tools, followed by OVL and PSL.
Here’s where the results get interesting. When asked what type of virtual- prototyping environments were currently being used, ARM was the favorite—but by a decreasing margin for future projects. Synopsys’ Virtio was the second most popular choice, showing projected growth along with Coware, VaST, and Virtutech (see Figure 5). One should exercise caution when interpreting these results, as the slower pace in the usage of ARM tools may simply ref lect the growth of virtual prototypes in non-telecom-related industries.
Looking at the other end of the prototyping spectrum revealed that Synplicity was used more often for ASIC prototyping with systems based on field-programmable gate arrays (FPGAs)—at least in the market areas highlighted by this study. ProDesign followed second and then came Dini and Gidel. It must be noted, however, that 36% of respondents still used custom-build FPGA-based prototyping. This percent was on the decline for future projects, however. Such a marked decrease in custom-build systems may attest to the growing complexity of ASIC designs and hence the corresponding complexity of FPGA prototypes.
Fig 5: Virtual-Prototyping Environments
This survey points to the changing dynamics in ASIC prototyping tools and methodologies. The prototyping of a specific block on an ASIC core now seems mandatory—especially because ASICs continue to increase in design complexity. This complexity is manifested by an increase in logical and functional errors in the chips, which has resulted in a need for more complete verification tools and methodologies. But prototyping itself has taken on a new dimension with the advent of virtual prototypes, which are used more often by software designers, and the FPGA-based prototypes used by chip hardware engineers.
These trends have been confirmed by other studies. For example, Aberdeen’s “Best in Class” study revealed verification as one of the most prevalent concerns in chip companies. Chip Design Trends reports, which track ASIC pre-silicon architectural trends, confirms the growing complexity of ASIC chips at all levels of design metrics. Contrast this complexity with the continued decrease in ASIC starts, and it seems that ASICs may be getting larger in size but less numerous in unique projects. All of these trends support the growth of prototyping as a key element in future chip designs.
On the business side of the equation, one should note the shift away from corporate electronic expenditures to the rapid increase in consumers’ consumption of electronic products. The consumer world is outpacing the corporate world in the purchase of electronic goods, but with this caveat: Consumer electronics have a shorter time to market and high product volume, but lower cost per unit than corporate electronics. What does this mean to chip designers? They must find a way to reduce ASIC respins, as they may with ASIC prototyping.
John Blyler is the Editorial Director of Extension Media, which publishes Chip Design and Embedded Intel® Solutions magazine, plus over 36 EECatalog Resource Catalogs in vertical market areas.