Economic, financial and competitive conditions are forcing ASIC and ASSP vendors to focus their efforts on very high volume markets and applications thereby creating a gap in the available technical solutions available to the markets being vacated by traditional silicon platforms.

As such, programmable devices are increasingly being used by electronics manufacturers of all types to fill this gap, according to Vin Ratford, Senior VP of World Wide Marketing and Business Development at Xilinx, Inc.

“Because the cost of an FPGA is amortized over multiple customers, we give just about anyone who wants it access to the latest process technologies…and with each new process technology, FPGAs deliver increased levels of performance at lower costs and with lower levels of power consumption,” he said.

Dr. Johannes Stahl, VP and GM of CoWare’s DSP Solutions Group has noted changes in the market as well. “The FPGA market is clearly poised to enable replacing a lot of SoCs and ASSPs by off-the-shelf FPGAs, which at the advanced silicon nodes will offer the complexity and power efficiency needed to support many applications in the consumer, automotive and wireless markets. Also in some of the traditional network infrastructure markets FPGAs can take on a bigger role through a combination of optimized signal processing IP blocks together with processors on a single chip.” An example for such a market is the upcoming LTE wireless standard.

To account for these changes, on the silicon side, Ratford remarked that Xilinx is continuing to drive down cost and power so that more applications can take advantage of FPGA technology, but there is a lot happening on the system, tool and IP side of the equation as well to give a broader set of designers the development flows they need to be productive.

“For example,” he continued, “the adoption of open standards, such as the FPGA Mezzanine Card (FMC VITA57) specification that defines high-speed I/O mezzanine card interfacing, and the AMBA standard for on-chip fabric communications, by FPGA vendors, IP and tool providers are also helping to bring programmable logic into the mainstream of system design.”

Stahl noted that the design of FPGAs at that level of complexity is no different than the design of complex SoCs, in particular, when the FPGAs carry processor cores. “With costs and risk associated with producing a mask set are gone for FPGA devices, the ROI for OEMs comes down to reducing the development cost for algorithm design, architecture design, software development, that occur on top of the traditional RTL development and backend design. While reprogramming FPGAs sounds conceptually attractive it is not a viable option to get to market fast enough. Therefore tools that apply for SoC/ASSP design and software development apply for FPGA in a similar way.”

“The market for Electronic System Virtualization (ESV) solutions that CoWare today sells into semiconductor companies and OEMs is still nascent for FPGAs,” he said, “and with the recent announcement of the industry leader Xilinx partnering with ARM to include ARM Cortex® Processors and related ARM interconnects on their chips, a direction is set, that will require wide spread adoption of ESV tools by FPGA customers over the next 2 years. ESV adoption for FPGAs will become the key enabler for FPGA companies going after SoC and ASSP sockets at major OEMs. System OEMs are investing today in ESV solutions that prepare them to take advantage of the broader range of silicon suppliers they can leverage with the advent of platform-based FPGAs.”

In terms of consultation and design services, Jim Henderson, president of Innovative Integration has seen a huge surge in the number of customers requesting these services in the early stages of projects to help accelerate customer product launches. “Typically, we are asked to simulate custom signal processing algorithms in Matlab, then embed the resultant code in Virtex 5 FPGAs. Usually, some C++ application code is also provided to create the infrastructure for the final application.”

Henderson has also noted a substantial upward trend in the number of customers requiring ruggedized FPGA-based products. “These customers typically required extended temperature operation, but mandate only middle-tier vibration and humidity levels,” he said.

From the perspective of Daniel Platzker, product line director of FPGA Synthesis at Mentor Graphics Corp. the biggest trends in the FPGA market are faster and bigger chips running with less power, along with shrinking schedules – all driven by the increased cost of ASIC development, increasing capabilities/capacity/speed/low power of FPGAs, shrinking development schedules, and the need to cut costs. “Many projects are converting from ASIC to FPGA. Users are now expecting tool robustness as with ASIC tools. Some applications that could only use ASIC can now be implemented in FPGA,” he said.

There are new FPGA vendors with niche capabilities such as more than 1GHZ clock and very low power as well as some FPGA-like designs with ASIC-like costs, Platzker pointed out. “What’s happening here is that some existing vendors and some new vendors are making it possible to use FPGAs, developed with FPGA design tools and with FPGA flexibility, as a starting point, and then once the customer has got the design set, the FPGA vendor will deliver an ASIClike chip. This gives the best of both worlds – the flexibility of an FPGA with ASIC-like pricing.”

Another driver for the increasing interest and use of FPGAs in place of ASICs or ASSPs is the fact that FPGAs have become much easier to develop as new, higher-level language-based development flows, leveraging C or Matlab for example, enable developers to approach FPGA development from a more familiar, abstract perspective, Ratford asserted. “Tools such as The MathWorks’ Simulink have the potential to provide a graphical-based object-oriented environment for FPGA development as well as the development of hybrid FPGA/processor-based systems. Tools are also being introduced that simplify the integration of multiprocessor systems,” he added.

Specific examples of new applications driving FPGAs in different markets are in automotive infotainment where designers are merging in-car access to rich media content typically found in the home with real-time access to road, traffic, and GPS information. Lane departure warning systems and driver fatigue sensing systems are other examples.

Outside of the automotive space, applications such as video surveillance and integrated analytics leverage FPGAs, along with wired and wireless communications, defense, medical and test and measurement applications – all use today’s FPGAs to address emerging and changing standards, while at the same time delivering the power, performance and feature requirements that only ASICs did in the past, Ratford said.

Henderson agrees that surveillance and military applications are driving trends in the FPGA industry, and has seen a surprising number of medical or mobile instrumentation applications.

Engineering Challenges

With the increasing use of FPGAs in a wide range of application, customer demands include tools and methodology for vendor-independent designs; making verification easier; complete flow integration including PCB-FPGA co-design; meeting QoR (mainly timing closure); IP integration; embedded software development; synthesis/PAR run time; and less design iterations, according to Platzker.

Henderson noted that since the current crop of highdensity FPGAs are power-hungry and run hot, customers request these devices be coupled with state-of-the-art analog I/O resulting in designs with very high power-densities. “Fortunately, the newly-announced Virtex6 devices will mitigate this issue,” he said.

Finally, in terms of engineering challenges that customers are asking to be addressed, Ratford pointed to the previously mentioned FMC standard, which he said is a great example. “Because FPGA I/O interfaces are tightly coupled to the device’s underlying architecture, circuit boards have to be designed specifically to handle a particular type of I/O, limiting the amount of reuse afforded to board designers. The new VITA 57 standard, also known as the FPGA Mezzanine Card (FMC), addresses this and other related I/O issues by defining an I/O mezzanine module that works intimately with an FPGA so that systems can be built modularly.”

“As today’s systems continue to drive more bit bandwidth, it’s important to customers that we enable efficient communications between chips on a board, between the cards and equipment that make up a system, and of course on the chip itself. Serial I/O adoption continues to increase, which is why Xilinx has included resources such as hardened PC Express blocks on their chips,” he continued.

“Likewise, customers are asking for more serial I/O and memory interface bandwidth on our chips because new applications require ever more memory interface bandwidth. We also need to keep up with cutting edge interface technology such as Interlaken, 100G+ Ethernet, streaming HD video, and so fourth…Power management is obviously critical. The FPGA industry continues to make improvements in the power consumption of our devices as customers require higher performance in smaller and smaller form-factors, and at the same time want to simplify heat sink and airflow. They also want to fewer and lower cost power supplies and many want to be Energy Star compliance. These are all issues you’ll be seeing the FPGA industry continuing to address in coming generations of products,” Ratford concluded.

Ann Steffora Mutschler is Editor of Extension Media’s EECatalog Resource Catalogs, and is also a Contributing Editor to Chip Design Magazine’s System-Level Design and Low-Power Design Communities. Her previous experience includes a long stint as a Senior Editor at Reed Business Information for publications including EDN, Electronic News and Electronic Business. She has moderated a number of panels in Silicon Valley and has written for publications worldwide.