Aldec supports OVM and UVM in Riviera-PRO



HENDERSON, Nevada – June 21, 2010Aldec Incorporated, an EDA leader in front end design and verification, unveils today its latest verification platform Riviera-PRO 2010.06. The latest release supports the Open Verification Methodology (OVM) co-authored by Cadence (NASDAQ:CDNS) and the early release of the next industry standard Universal Verification Methodology (UVM) from Accellera.   OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities. Riviera-PRO 2010.06 provides a pre-compiled OVM library and SystemVerilog simulator to help customers take advantage of this powerful design verification methodology to meet the challenge of verifying today’s complex designs. OVM has reached a level of maturity and stability and is the basis for the UVM assuring the long-term popularity and resulting in an increased support demand in a wide variety of tools.    

Users of different levels of expertise can rely on OVM to quickly build up a layered, coverage driven, transaction-level verification environment that can be reused across different designs and different platforms. Verification engineers will appreciate the flexibility OVM gives them and hardware designers will be satisfied that they can do advanced verification without going through advanced SystemVerilog training.

 “Cadence leads both OVM and UVM development to raise verification productivity throughout the industry,” said Adam Sherer, Cadence Design Systems, Inc., verification product management director.
“We welcome Aldec to the growing list of RTL simulation vendors in the ecosystem supporting the methodology common to both OVM and UVM, and we look forward to further adoption by the entry and middle-tier FPGA developers served by Aldec.”

Riviera-PRO 2010.06 provides a unique approach to front end design, simulation and debugging of FPGA and ASIC devices. Riviera-PRO supports the most advanced verification methodologies, including ESL, TLM, and Assertion-based verification.  The product includes advanced debugging tools, code coverage and a performance waveform toolset.  Riviera-PRO is a multi-platform simulator, supporting 32 and 64 bit CPU architecture, Windows® 7, Vista and XP and Linux. 

Availability
Riviera-PRO 2010.06 is available today and sold directly from Aldec and its authorized world-wide distributors. For more product information or to download a free evaluation copy, visit www.aldec.com

About Aldec
Aldec Incorporated is an industry-leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

Media Contact:
Lori Nguyen
Director of Marketing
Aldec Incorporated                                
(702) 990-4400, ext.254 
Lorin@aldec.com

Riviera-PRO and Aldec are trademarks of Aldec Incorporated. All other trademarks or registered trademarks are property of their respective owners.

Contact Information

Aldec, Inc.

2260 Corporate Circle
Henderson, NV, 89074
USA

tele: 702-990-4400
fax: 702-990-4414
sales@aldec.com
www.aldec.com

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