FPGA Highs and Lows (Density, That Is)



FPGAs are spanning a much broader array of applications these days, from ultra-low-power mobile devices through demanding “heavy iron” designs.

A recent market report by Transparency Market Research forecasts healthy growth in the FPGA market, from USD 5.08 billion in 2012 to USD 8.95 billion by 2019—a CAGR of 8.5% from 2013 to 2019. Drivers include LTE adoption and the need for high bandwidth in wireless networks, as well as the use of FPGAs in mobile devices such as smartphones, tablets, and growing electronic content in vehicles. Our roundtable panel addresses the full spectrum of FPGA applications, challenges and new technologies. Thanks to Dave Myron, senior director of FPGA product management and marketing for Xilinx; Joy Wrigley, senior product line manager of ultra-low density products at Lattice Semiconductor; and Paul Karazuba, senior product marketing and media manager at QuickLogic.


EECatalog: How are today’s FPGAs being implemented in low- and ultra-low-power applications? Are I/Os the choke point for these designs?

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Dave Myron, Xilinx: FPGAs are designed into almost every conceivable application and it is rare that power alone is the primary design concern. Although power considerations have indeed been moving to the forefront as one of our customers’ key design concerns, performance, footprint, BOM cost and system integration all weigh in with their own level of importance. The weighting for all of these design characteristics varies by the overall objectives of the end application and the design team’s goals. It would be hard to say that any one attribute—such as I/Os—serve as the choke point for designs where power consumption is the primary concern. For power-sensitive DSP or compute-intensive designs, I/O counts aren’t really a factor. Conversely, I/O-bridging designs can indeed be pin-limited. Power alone usually plays less of a role with respect to I/O pin limitations.

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Joy Wrigley, Lattice Semiconductor: Across many markets, I’d have to say that Lattice FPGAs are taking on new functions and applications that are being defined by the innovation and new ideas generated by mobile. Bridging, I/O expansion, hardware acceleration, command and control and time-critical parallel processing are the bread and butter FPGA functions within these low-power and ultra-low power applications. At the end of the day, these are the traditional functions that FPGAs have always supported. What is being augmented to the traditional role of FPGAs, and what’s really exciting for us at Lattice, is the fact that mobility is becoming the hotbed of innovation, which means battery power is the key design constraint for many of today’s new products and applications.

By the nature of the low- and ultra-low power applications our customers are building, Lattice is seeing our devices used in completely new functions that few had ever envisioned before. One of the most recent trends is in the area of context-aware, always-on applications using multiple sensors. For example, data from a gyroscope, accelerometer and magnetometer might be used together in a smartphone or tablet to create an inertial navigation system.

Also, by having incredibly small FPGAs we are finding ourselves in completely new applications that value space as well as power and cost. As an example, if you look at a gas or water meter, it’s an incredibly tiny, complete system that needs to successfully complete multiple functions, including connectivity, and there’s no room for 10 or 15 chips that would typically support this. You need a product that can do a little bit of everything. There are areas throughout the embedded space that are getting smaller and more thermally constrained and Lattice is unique to solving these problems.

As far as the I/0 is concerned, it depends. Power, size and functionality are really the choke points we see. We offer a wide range of I/O, so this isn’t always an issue for the sockets we’re filling.

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Paul Karazuba, QuickLogic: Today’s low and ultra-low-power FPGAs are being utilized greatly for bridging and I/O interfaces such as I2C, SPI, UART, SDIO and the local bus of various application processors. Low-power FPGAs are uniquely suited for the expansion of interfaces for connectivity and in some cases, co-processing. I/Os remain a choke point for designs, specifically in mobile form factor designs, although a larger factor when using low-power FPGAs is finding a balance between having enough logic for the required application and fitting in the mechanical size desired.


EECatalog: Can low-power and ultra-low-power FPGAs offer competition to MCUs for sensor fusion?

Myron, Xilinx: FPGAs and all-programmable SoCs (Zynq) offer significant competition to MCUs today in the area of sensor fusion. As an example: advanced driver assistance system (ADAS) platforms based on Xilinx Zynq All Programmable SoCs fuse multiple imaging and LIDAR sensors to perform a wide range of functions that include lane departure warnings, pedestrian detection and calculating vehicle distance. The performance requirements for these tasks far outstrips the computational capabilities of today’s MCUs and requires the significantly higher pixel-processing at rates that can only be supported by the parallel processing engines made possible by the resources found in programmable logic.

Wrigley, Lattice: Absolutely. If you take a step back and look at what’s needed in those applications, both can exist very well as stand-alone options, or complementary options. Again it gets back to what you are trying to accomplish. When it comes to acceleration/expansion/bridging, the FPGA always lends itself exceptionally well. You may be able to squeeze everything into a processor, however if you’re looking for size, power and performance, an FPGA can complete a fixed number of tasks superior to a processor. It’s like the processor is a generalist, but an FPGA can do functions exceptionally well. No one size fits everything.

You can have the FPGA do everything, or the processor do everything, or they can share the load. Each of these scenarios has their benefits. The trick is to pick the tasks and functions that require the fastest response time, zero latency and really low power—stick those in the FPGAs. The trick is to do a little as possible in the processors in order to avoid thermal, power and I/O limitations.

Karazuba, QuickLogic: Absolutely. Ultra-low-power FPGAs, like those from QuickLogic, can perform all the sensor fusion functions of MCUs at a fraction of the power consumption (1/30 in some cases). This can be done without any negative effects on contextual awareness, as well as (most importantly) user experience.


EECatalog: How do MIPI and other standards fit into FPGA vendor roadmaps?

Myron, Xilinx: While MIPI was first introduced several years ago primarily as a connectivity interface for mobile devices, it is clear that this interface is now gaining broader adoption across a much wider range of markets and applications. MIPI’s lower signal-swing technology—optimized for short-reach connectivity—provides an attractive lower-power alternative for very high-bandwidth interfaces in many applications as long as the signals aren’t required to travel long distances. For this reason, we are now seeing a range of devices and sensors ranging from ASSPs targeting communications markets to 4K/2K camera sensors all adopting MIPI connectivity. It’s not uncommon to see a connectivity standard that was originally developed for one market see broader adoption across multiple markets. The R&D leverage that is derived from using an industry standard versus a unique, proprietary standard can be quite compelling. For example, low-voltage differential signaling (LVDS) was originally defined for the notebook PC market to allow for efficient, low-EMI transport of video signals from PC motherboard to LCD screen in laptop computers. Today, the LVDS interface is employed in almost every conceivable market. Today’s FPGAs already support MIPI signaling and you can expect that they will continue to support MIPI and a whole host of emerging and evolving standards. I/O programmability and the ability to support multiple signaling standards is a unique and fundamental FPGA capability that will continue to be critical to the success of FPGAs across broad markets.

Wrigley, Lattice: At Lattice, we understand bridging, expansion, acceleration and so forth are fundamental applications that bring value to our customers. All standards including MIPI are central to the capability to offer complete solutions with our support of our entire ecosystem that includes IP vendors, board vendors, EDA vendors, distributors and so on. MIPI in particular is interesting because it’s an evolving standard that’s coming out of the mobile space and being applied across many markets. Given our exposure to the consumer mobile space, Lattice is uniquely positioned to provide MIPI solutions involving DSI and CSI-2, for example, across a wide variety of non-consumer applications. At the end of the day, we excel at bridging new interface standards such as MIPI to traditional standards with the lowest size, power, cost and performance.

Karazuba, QuickLogic: Interface standards will always maintain a high importance on vendor roadmaps, as I/O connectivity remains an important function for FPGAs. However, MIPI, due to its high speeds and requirements for PHYs, may not make the most sense to be done in programmable fabric versus hard logic.


EECatalog: The IP ecosystem is necessary in FPGAs used as bridges between standards such as MIPI, PCIe Gen 1 and 2, etc. What’s happening in the ecosystem to support this?

Myron, Xilinx: We continue to see an-ever expanding ecosystem of IP suppliers committed to supporting current and emerging connectivity standards. The market for IP suppliers that support a wide range of functions including connectivity continues to grow as FPGAs continue to expand their reach into a growing range of applications.

Wrigley, Lattice: An FPGA vendor by definition needs to work with many technology providers. As I mentioned earlier, IP is just one component of the ecosystem for us as we offer complete solutions that include boards, reference designs and of course development tools.

From the Lattice perspective, we see the appropriate ecosystem support as critical for enabling us to support the rapid development cycles customers are facing. We see three different activities that are very important.

  1. Providing IP, often free, that supports interfaces and standards that have to be tightly coupled with our silicon, such as MIPI or PCIe.
  2. Participation in key standards groups such as the MIPI Alliance.
  3. Choosing critical functions and finding partners for implementing the IP.

Karazuba, QuickLogic: The rapid speed of development of mobile devices has allowed some IP for mobile-centric interfaces such as MIPI to become available quicker than in the past. However, that rapid development can lead to situations where IP, once openly commercially available, may already be a generation or more behind the leading-edge developers.


EECatalog: Recent ARM/FPGA SoCs have opened up new opportunities for Linux programmers. What changes do you expect to see in embedded designs to take advantage of this?

Myron, Xilinx: The introduction of the Xilinx Zynq All Programmable SoC has been a key industry innovation that has already seen very wide adoption across a wide range of markets and applications in a relatively short period. Well before the introduction of Zynq, system architects grappled with the challenges associated with two-chip solutions that married an embedded processor to an FPGA. System architects prefer to solve their problems using only one device if at all possible for reasons including BOM cost, design simplification and footprint. Additionally the system architect would like to be able to seamlessly partition their design between hardware and software making performance/area tradeoffs throughout the design cycle. If at all possible, system designers would also like to view hardware accelerators as memory-mapped functions without any consideration or need for understanding the underlying programmable logic used to implement these accelerators. Ideally, changing the design boundaries between hardware and software should not mandate PCB re-design. Through a combination of the Zynq All Programmable SoC—which combines a dual-core ARM Cortex-A9 MPCore processor with high-performance Xilinx 7-series programmable logic—and the supporting Vivado Design Suite—which includes high level synthesis, HLS, which complies C language to FPGA gates—system architects can now achieve the above design goals in the ideal world. The Zynq SoC’s potent combination of processors, silicon and software opens up the world of high-performance processing using All Programmable SoCs to embedded programmers through a wide range of embedded operating systems including Linux.

Karazuba, QuickLogic: With the addition of new resources and better development environments for Linux on ARM/FPGA SoCs, it is expected that embedded designs will continue to see faster system responsiveness and better use of real-time applications. Time-critical applications such as disaster monitoring, spatial awareness and precise gaming will be more readily available.


EECatalog: Intel’s X1000 “Quark” SoC is an x86 low-power core that can be instantiated in Intel’s (and theoretically, other’s) design rules. If available, would it be a probable core to include in an FPGA as an alternative to ARM such as in Zynq?

Myron, Xilinx: While processor size, performance, power efficiency are important factors when considering the potential for integration in an FPGA, equally as important is the supporting ecosystem, which not only includes the breadth of the ecosystem but also the alignment of the ecosystem to the embedded markets where all-programmable SoCs are being employed. While Intel is clearly making strides with the introduction of Quark, ecosystem support and the alignment of the ecosystem will play a key role in consideration as a candidate for integration. While Xilinx cannot speculate on Intel’s future plans for the Quark synthesizable processor, others have: http://seekingalpha.com/article/1792672-intel-wont-build-arm-mobile-chips

Wrigley, Lattice: We expect FPGAs to continue to coexist with processors for some time to come. One of the most common applications that our FPGAs are used for is I/O expansion and hardware acceleration for MCUs and microcontrollers. Our view is that the industry has yet to define a good integrated architecture that combines FPGAs and processors on a single piece of silicon. As is often the case, these solutions are miss-optimized or not optimized for the vast majority of applications. We continue to look, but we don’t see the answer. We do see continued interest in soft processors and we are happy with the uptick of designers using either the LatticeMico8 or LatticeMico32 open source processor cores. We understand that customers are going to invest a lot time in resources building their own proprietary architecture based on our technology, which is why customers can utilize our soft cores and take them to ASIC afterwards if they want.

Karazuba, QuickLogic: If available, it is definitely probable that the Intel X1000 SoC could be integrated with the programmable fabric of an FPGA. The limiting factor is being able to fit the components together, while keeping the power consumption, and physical dimensions within the requirements of designers.

Providing an ARM core in an FPGA or an FPGA-based processor is fine only if it can be used effectively in the system. System integration involves collaboration between hardware and software engineers. Success lies in the tools and support (provided by the hardware vendors) that enables this collaboration to take place, and often times that means making the programmable hardware appear more like a traditional processor development flow.


EECatalog: How will high- and low-density FPGA manufacturers compete moving forward?

Myron, Xilinx: High-density and low-density FPGAs focus on delivering the right mix of features, performance and power, at the right price. Productivity both through software tools and IP solutions also plays a key role in affecting the customer’s decision. Today’s largest programmable-logic devices, which contain as many as two million logic cells, require ASIC-strength design tools to place and route large designs and to achieve requisite quality of results (QoR). The silicon, software, IP and technology investments required to deliver today’s high-density programmable-logic devices can only be realized through leading-edge (or bleeding-edge) process technology including stacked silicon interconnect technology (SSIT) and require financial commitments and technical acumen that dissuades new players from entering these markets.

Wrigley, Lattice: In many case they won’t because markets are diverging. What we at Lattice have learned is that high-end and low-end customer needs are completely divergent, and as everyone knows, you can’t scale one architecture to serve both high-end, low-end and ultra-low-end. This is particularly the case for consumer and similar applications where the FPGA power consumption has to be in the micro-watts, and have to use low-cost, small WLCS packaging. It’s also the difference between traditional ‘heavy-iron’ applications the high-end serve and the newest gadgets that are selling to consumers in the millions of units every day.

Increasingly at Lattice we’re not seeing the other FPGAs as competition as we continuously drive to the lowest cost and size. For the implementation of functions that we commonly tackle, we’re seeing our customers consider Lattice FPGAs as more flexible alternative to micros and ASSPs.

Karazuba, QuickLogic: High- and low- density FPGAs will continue to serve mostly separate markets. High-density FPGAs will continue to well serve the industrial, scientific and aerospace markets, whereas low-density, low-power FPGAs will continue to expand I/O connectivity and sensor hub applications in mobile devices.


Cheryl Berglund Coupé is managing editor of EECatalog.com. Her articles have appeared in EE Times, Electronic Business, Microsoft Embedded Review and Windows Developer’s Journal and she has developed presentations for the Embedded Systems Conference and ICSPAT. She has held a variety of production, technical marketing and writing positions within technology companies and agencies in the Northwest.

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