FPGAs and SoCs are destined to have a working relationship that gets ever closer, something applications that range from aerospace to virtual reality to machine learning won’t mind at all.
Nishant Mittal, Systems Engineer at Cypress Semiconductor, explains how the growing demand for miniaturization is intertwined with the increasing popularity of SoCs. In this issue Mittal discusses SoCs in the context of such goals as keeping power consumption to a trickle, isolating noise, and optimizing speed. He doesn’t minimize the challenges, but his article also includes descriptions of such tools as drag and drop GUIs that can make developers’ tasks easier, as can the ability to program SoCs to go for power efficiency over performance and vice versa.
While wearables and smartphones have been pressing for miniaturization, individuals advocating for More Electric Aircraft (MEA) are urging power electronics to become more reliable, integrated, and higher performing. Shane O’Donnell, manager for Microsemi Corporation’s Aviation Center of Excellence, recently participated, along with Microsemi CTO Jim Aralis, in an EECatalog Q&A. O’Donnell wants aerospace manufacturers to examine what newer technologies, including wide bandgap (WBG) semiconductors can bring to the party when the objectives are improved performance, size, weight, and reliability. He tells us about the company’s Power Core Module and about the benefits that occur when SiC MOSFETs replace Si IGBTs. Aralis discusses the greater number of roles FPGAs are taking on—coprocessors in data centers; voice recognition; server applications for baseband generation—as FPGA performance improves. For aircraft, Aralis notes, having “the system on a chip inside an FPGA “can make possible the processing power needed, for example, to optimize a jet engine “on a very quick cycle.”
The bridge game designers play today involves those legacy systems, which, Grant Jennings reminds us in this issue, can include I/O which runs the gamut from “legacy CMOS and proprietary interfaces to source synchronous standards to interfaces that feature an embedded clock for larger systems.” Jennings, a Senior Strategic Planning Engineer for Lattice, goes on to explain that systems today have a great number of potential bridging applications. He makes the case for considering an alternative to a “one-size-fits-all” approach.
Also on the topic of connections, Executive Editor Lynnette Reese writes here about a means to achieve higher throughput and lower latency: Remotely connect FPGAs through PCI Express over cables or between backplane segments. Reese spoke with Dolphin Interconnect Solutions about how that company is applying technologies such as device lending and multi-cast to improve the outlook for real-time imaging, time-sensitive transactions, and more.
How we’re going to cross the bridge from Artificial Intelligence (AI) and machine learning experiments to accelerated adoption and monetization of these technologies is the topic of the article by Sylvain Dubois, Crossbar, this month. And it is not just bridges, but bottlenecks, that are on Dubois’s mind as he explains that an approach to taking on today’s processor memory bottlenecks begins with “memory technologies that can be directly integrated on-chip with the processing logic” to realize memory-centric SoC architectures.
Integration that has been the cause of some anxiety among designers, that of Altera with Intel, is one topic our Technology Editor Dave Bursky addresses here. Bursky summarizes for us the presentations Intel gave at the 2016 IDF, where the company revealed its product development directions and both software and hardware applications of Intel Programmable Solutions Group FPGAs.
Revelations in the form of news, videos, white papers, opinion and articles is waiting for you at http://eecatalog.com/fpga and all our channels.