Distributed PLD Solution Reduces Server Costs and Increases Flexibility



Take advantage of resources for getting systems into varied markets even while facing tight time frames.

Servers come in many different types—from rack and blade versions to tower and modular configurations for high-density computing. Ideally, each server is optimized to perform its specific task. On closer observation, however, most server designs share a number of common characteristics. Typically, they feature multiple processors, hot swappable storage, a wide range of peripherals connected to the CPU and the Platform Controller Hub (PCH) via PCI Express (PCIe), security services, and power management resources— to name just a few common elements. So, while designers appear to create very different solutions for different applications, in most cases they are customizing a basic server architecture.

Figure 1 illustrates this common server architecture. More often than not, server designers customize this basic architecture to meet the needs of different markets. The use of peripheral hardware blocks, system level interface blocks, baseboard management controller (BMC) interfaces, and other key components may vary from one server design to another.

Figure 1: Server block diagram with 8 PLD use cases

The power management, control and glue logic function block consistently plays a key role in the customization of a design to meet specific application requirements. Designers need to modify functions such as power management, board specific glue logic, or I/O expansion for each server type. Historically, designers have opted for implementing the power management, control and other glue logic functions using many types of discrete components. For many years, that approach offered the more cost-effective path. Today, designers who are using the discrete approach to design modern servers end up spending more time and resources modifying their design to meet the needs of multiple server types. Consequently, modern servers use a PLD to integrate power management, control and glue logic.

Eight PLD Use Cases
The eight PLD use cases (Figure 1) discussed here include implementation of power management and other control functions of main server board, as well as in add-on cards, protection of the board firmware against malicious attacks, and other glue logic integration. Typically, single-rail, instant-on, non-volatile PLDs (e.g., Lattice MachXO3 devices) are used to integrate discrete function ICs. This enables the control portion of the server circuit to be operational before any of the large devices, such as CPU and PCH, are on.

Power Management, Telemetry, Control and Glue Logic Functions
In Figure 2a the control PLD device is used for the implementation of functions, such as power/reset sequencing, various types of serial busses (I2C, SPI, eSPI, SGPIO, etc.), debug ports, LED drives, FAN PWM driver, front panel switches sensing and other general GPIO functions. In general, the Control PLD in use case 1 (Figure 1) is I/O intensive.

Servers are required to measure onboard supply voltages, board and device temperatures. Typically, to maintain good measurement accuracy, Analog to Digital Converter (ADC) ICs are used to measure the voltage rails located far away from the BMC on a server board. A number of temperature sensing ICs measure the board temperature at various locations for thermal management.

Figure 2a/2b (left to right): Traditional control PLD (use case 1 on Figure 1; Overall lower cost control PLD circuit with power down sequencing support (use case 4 on Figure 1)

In the current server design, the control PLD uses the ‘Power Good’ and ‘Enable’ signals from Point of Load (POL) supplies to implement power sequencing. But the ‘Power Good’ signal alone is not sufficient for reliable implementation of power-down sequencing.

The Analog Sense and Control (ASC) IC (Figure 2b; use case 4 on Figure 1) addresses the power-down sequencing problem by providing the important power-off status (Rail Voltage < 100mV), in addition to ‘Power Good’ status to the Control PLD through a serial bus. The ASC device reduces overall bill of materials (BOM) and cost by integrating the ADC function and multiple temperature monitor ICs. In addition, the ASC IC offloads the number of I/Os from the CPLD. These spare I/Os on the control PLD can be used to integrate on-board I2C buffer ICs and I2C multiplexer ICs, reducing the BOM and cost further.

Logic Functions Needed to Support Hot Swappable Disks
Rack servers support hot swappable HDD/FD/NVMe drives (use case 2, Figure 1). These disk drives are plugged into a backplane. The backplane interfaces to the main motherboard through serial interfaces, such as SGPIO and I2C. A control PLD can be used to integrate the logic functions required on a backplane control. For example, when an NVMe drive is plugged into the drive slot, the logic in the device will automatically route the status and control signals to I2C bus instead of SGPIO bus.

Hardware Management of Host Bus Adapter Board
Another potential application for the control PLD devices is in the integration of host bus adapter control logic (use case 3, Figure 1). This device also integrates SGPIO and other out-of-band signaling, manages power/reset sequencing and other PLD functions, including fast supply fault detect, and status save.

BIOS and BMC Firmware Authentication
To prevent malicious access into BIOS and BMC firmware a CPLD device can serve as a hardware authentication device (use case 5, Figure 1). In this configuration, these devices can be used to validate the system BIOS and BMC firmware using Elliptic Curve Signature Authentication. They can also be used to manage automatic golden image switchover in the case of a compromised active image.

Bridging Between TPM/ TCM and Single SPI Interface on PCH
Server designers can use CPLD devices to bridge between a PCH serial peripheral interface (SPI) interface with an LPC interface of TCM chip on a module (used in China) or directly plug in a TPM module (used anywhere outside China). This enables easy customization of the same server platform for all regions of the world (use case 6, Figure 1).

Integrating Multiple Functions on Riser Cards
Servers typically use riser cards to connect LED drive, control, and enclosure sense functions on a riser card to reduce the number of interconnections on the main board (use case 7, Figure 1). Often, these functions are implemented using discrete logic ICs, which results in multiple types of riser cards, each with slightly different functionality. An option to reduce the number of riser cards types is to integrate the functions for each of the cards onto a control PLD. One can then customize the logic on the card by simply modifying the logic integrated in the device during manufacturing.

Integrating Multiple I2C Buffers
The CPU in a server system communicates with the DDR memory DIMMs on either side via a pair of I2C buffers (use case 8, Figure 1 and Figure 3). The CPU also monitors the SSD drive through another I2C interface. Designers are required to use voltage level translator buffers to map the CPU’s 1.05 V I2C interface with the DDR memories operating with 2.5 V and the SSD drives operating at 3.3 V. The CPU also generates multiple out-of-band signals using a 1.05 V logic signal interface. These out-of-band logic signals are required to communicate with other devices operating with a signal interface of 2.5 V or 3.3 V. This requires using GTL (Gunning Transceiver Logic) buffers on the board.

Figure 3: CPLD integrates multiple I2C buffers and GTL buffers

Low cost CPLDs such as the Lattice MachXO3 devices in a small QFN package (5mm x 5mm) can be used to integrate level translation from 1.05 V I2C and other logic signals to 3.3 V and 2.5 V. This reduces the circuit board area, BOM, and, more important, the cost to implement this functionality.

Conclusion
Today’s server designers are constantly trying to pack more functionality on their boards as quickly and cost-effectively as possible and release systems for multiple markets with minimum time delay. Using control PLDs instead of traditional discrete solutions is one of the best ways to meet this demand. By offering designers a simple way to integrate all control path functions into a single programmable device, and by adding new capabilities that allow designers to modify designs even after they have shipped to the field, control PLDs such as Lattice MachXO2 and MachXO3 devices promise to significantly simplify board design and debug while reducing overall BOM cost through integration.


Srirama (Shyam) Chandra is a senior marketing manager for programmable mixed-signal products at Lattice Semiconductor. With over 15 years of experience of working with programmable logic devices and power management products, he offers expert industry knowledge, and is a widely published author and recognized authority on power management. Prior to joining Lattice, Mr. Chandra worked for Vantis and AMD in sales and applications, and was also a telecom design engineer with Indian Telephone Industries. Mr. Chandra received his bachelor’s degree in electrical engineering from Bangalore University and master’s degree in electrical engineering from the Indian Institute of Technology, Madras.

 

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