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  • TI E2E Community

    TI E2E Community

    Blog Post: FPGA power made simple: design steps
    Published. November 20, 2017

    Over the last three installments of this series, I have gone over some basic design considerations for creating a power supply for field-programmable gate arrays (FPGAs). Now that you have determined the power requirements and identified some necessary feature and performance specifications, you are ready to pick parts! One way to simplify FPGA power if you are a new designer (or strapped for time) is to choose modules as your power supplies. Modules integrate the inductor as well as other passive...


  • Jack Erickson's Blog

    Jack Erickson's Blog

    What's For Breakfast? Video Preview November 27th to December 1st 2017
    Published. November 20, 2017

    https://youtu.be/AMMOBeri5E8 Coming from building 10 fussball table (camera Sean) Monday: What's the Difference Between MOESI and MESI? Cache-Coherence for Poets Tuesday: CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper Wednesday: Chips and Technologies: The First Fabless Company Thursday: JUG Invited Presentations Friday: Silexica: Mastering Multicore www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email....


  • Jason Andrews Blog

    Jason Andrews Blog

    What's For Breakfast? Video Preview November 27th to December 1st 2017
    Published. November 20, 2017

    https://youtu.be/AMMOBeri5E8 Coming from building 10 fussball table (camera Sean) Monday: What's the Difference Between MOESI and MESI? Cache-Coherence for Poets Tuesday: CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper Wednesday: Chips and Technologies: The First Fabless Company Thursday: JUG Invited Presentations Friday: Silexica: Mastering Multicore www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email....


  • Joseph Hupcey Blog

    Joseph Hupcey Blog

    What's For Breakfast? Video Preview November 27th to December 1st 2017
    Published. November 20, 2017

    https://youtu.be/AMMOBeri5E8 Coming from building 10 fussball table (camera Sean) Monday: What's the Difference Between MOESI and MESI? Cache-Coherence for Poets Tuesday: CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper Wednesday: Chips and Technologies: The First Fabless Company Thursday: JUG Invited Presentations Friday: Silexica: Mastering Multicore www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email....


  • Michael Jacobs Blog

    Michael Jacobs Blog

    What's For Breakfast? Video Preview November 27th to December 1st 2017
    Published. November 20, 2017

    https://youtu.be/AMMOBeri5E8 Coming from building 10 fussball table (camera Sean) Monday: What's the Difference Between MOESI and MESI? Cache-Coherence for Poets Tuesday: CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper Wednesday: Chips and Technologies: The First Fabless Company Thursday: JUG Invited Presentations Friday: Silexica: Mastering Multicore www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email....


  • Tom Anderson's Blog

    Tom Anderson's Blog

    What's For Breakfast? Video Preview November 27th to December 1st 2017
    Published. November 20, 2017

    https://youtu.be/AMMOBeri5E8 Coming from building 10 fussball table (camera Sean) Monday: What's the Difference Between MOESI and MESI? Cache-Coherence for Poets Tuesday: CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper Wednesday: Chips and Technologies: The First Fabless Company Thursday: JUG Invited Presentations Friday: Silexica: Mastering Multicore www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email....


  • Stephane Boucher's DSP Blog

    Stephane Boucher's DSP Blog

    Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
    Published. November 14, 2017

    This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with  application  examples will be maintained on the project website...


  • Tech Deseign Forums Blog

    Tech Deseign Forums Blog

    Microsemi sets up RISC-V partner program
    Published. October 19, 2017

    Microsemi has set up an ecosystem program around the RISC-V soft cores the company has designed for its FPGAs....


  • Electronics Engineering Video Blog Podcast

    Electronics Engineering Video Blog Podcast

    EEVblog #1029 – BGA PCB Fanout
    Published. October 6, 2017

    Dave looks at some issues with fanning out tiny 0.4mm pitch BGA packages, via pad and hole size, tenting, breakouts, solder mask expansion etc. And then compares it with an 1136 pin Xilinx Virtex 5 FPGA with 1mm pitch to show the difference in PCB process technologies needed. Forum HERE...


  • Steven Brown's Blog

    Steven Brown's Blog

    When Arm meets Intel – Overcoming the Challenges of Merging Architectures on an SoC to Enable Machine Learning
    Published. September 25, 2017

    As the stakes for winning server segment market share grow ever higher an increasing number of companies are seeking to grasp the latest Holy Grail of multi-chip coherence. The approach promises to better enable applications such as machine learning, network processing, in-memory data base, and other large dataset tasks. Arm and its partners continue to pursue the server market long dominated by Intel. The results will be SoCs that combine Arm CPU sub-systems with high speed interfaces such as PCI...


  • All About Microsoft

    All About Microsoft

    Microsoft shows off Brainwave 'real-time AI' platform on FPGAs
    Published. August 22, 2017

    Microsoft is sharing more details about its plans for bringing its deep-learning platform to customizable chips -- a step toward making Azure an 'AI cloud.'...


  • Analog Insights

    Analog Insights

    AMS SIG India, 2017 – Update
    Published. March 22, 2017

    Happy Wednesday folks! If you recall, AMS SIG India was held in Bengaluru last month (2/16/17). It was well attended and quite successful! Distinguished speakers from Samsung, Xilinx, Qualcomm, STMicroelectronics, and Synopsys R&D, spoke on a wide variety of topics centered around the use of Synopsys solutions to address AMS custom design and verification challenges […]...


  • Verification Horizons Blog

    Verification Horizons Blog

    Part 8: The 2016 Wilson Research Group Functional Verification Study
    Published. October 4, 2016

    ASIC/IC Resource Trends This blog is a continuation of a series of blogs related to the 2016 Wilson Research Group Functional Verification Study (click here).  In my previous blog (click here), I focused on FPGA design and verification trends.  I now will shift the focus of this series of blogs from FPGA trends to ASIC/IC […]...


  • Frank Schirrmeister Blog

    Frank Schirrmeister Blog

    Accelerating the Next Big Shift in Verification
    Published. September 8, 2015

    Today Cadence announced that we are aligning our proposal to the Accellera Portable Stimulus Working Group (PSWG) with the other two commercial vendors in this market – Mentor Graphics and Breker – to deliver a joint contribution, intended to accelerate the standardization process. More on this below. We at Cadence believe that portable stimulus standardization will be the hallmark of next generation verification automation. Looking at a recent key-note at CDNLive India, Samsung seems to agree...


  • Ran Avinun's Blog

    Ran Avinun's Blog

    Comment on Why the Demand for Acceleration and Emulation is Growing
    Published. February 27, 2011

    FPGA prototyping systems are very important and are complementary to emulation systems. They are being used mostly when the design is matured and the numbers of iterations is small. The main use model for FPGA prototyping is software development and exhaustive regressions with focus on emulation replicates running at high performance. Emulation is being used earlier in the design phase mostly for system validation with focus on HW and SW debug and advanced verification acceleration as an expansion...


  • Adam Sherer Blog

    Adam Sherer Blog

    Harris-Cadence-Mathworks-Xilinx Success Cuts Verification Time 85%
    Published. April 29, 2010

    More and more often it takes a village to achieve verification success. As reported recently by MathWorks, Harris pulled together technology and support from Cadence, MathWorks, and Xilinx to cut their verification time by more than 85% and achieve a defect-free FPGA implementation. “EDA Simulator Link provided a direct co-simulation interface between our MATLAB model and our logic simulator , which enabled us to verify our design earlier, identify problems faster, complete more tests, and compress...


  • Denali Memory Blog

    Denali Memory Blog

    MIPI DevCon 2016 – Mobile and Beyond
    Published. August 21, 2016

    MIPI DevCon 2016 – Mobile and Beyond The word “beyond” may bring up thoughts of the new Star Trek Beyond movie, or for those of you who are fascinated by real space travel, the National Aeronautics and Space Administration (NASA). Maybe that’s why the first MIPI Alliance® Developer’s Conference will be held in, Mountain View, California, near the NASA Ames Research Center. The real lesson to be learned is how the MIPI protocols, conceived to standardize chip-to-chip...


  • Team Specman Blog

    Team Specman Blog

    DVCon 2013 for the Specmaniac
    Published. February 7, 2013

    At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and e language-related content, or be of general relevance to Specmaniacs. Hence, if you are going to the conference, please consider printing out the following "DVCon 2013 Guide for the Specmaniac"....


  • Team ESL Blog

    Team ESL Blog

    More Details on Post Silicon Embedded Software Verification With ISX
    Published. August 18, 2009

    Please welcome back Joerg Simon and Markus Winterholer, both from the ISX team in Germany, to the TeamESL blog for the next installment on post-silicon embedded software verification with ISX. This post is a discussion featuring Markus and Joerg talking to Malte Henzelmann and Ernst Zwingenberger of El Camino GmbH . It builds on the introduction that was provided in June titled OVM Metric Driven Verification with an FPGA-based Design . You guys built a cool demo connecting ISX to a FPGA board for...


  • Signal Integrity

    Signal Integrity

    Practical Approach for Signal Integrity Analysis of High Data Rate Channels Free One – Hour Webcast in July
    Published. June 29, 2016

    Keysight EEsof EDA’s Tutorials in Signal Integrity webcast series is important to Signal integrity engineers who may not have the time or budget to attend continuing education classes on the latest design tools and techniques. This webcast highlights various technologies used for channel modeling, each with advantages and disadvantages, by utilizing real-world FPGA board routing and […]...


  • NextGenLog

    NextGenLog

    #NEWS #China One-Ups #Apple with Gas Sensors in Cheap iPhone Knock-Offs
    Published. November 6, 2015


  • A View From the Top

    A View From the Top

    Introducing HAPS-80 FPGA-Based Prototyping Solution
    Published. September 28, 2015

    In this month’s blog I would like to focus on a recent prototyping solution announcement from Synopsys. On September 16, Synopsys announced the new HAPS-80 FPGA-based prototyping systems, part of Synopsys’ end-to-end prototyping solution strategy. As software is now driving the main capabilities of embedded devices, it has taken the spotlight in SoC design.  This […]...


  • scalability.org

    scalability.org

    M&A: Avago grabbed Broadcom, Intel grabs Altera
    Published. June 1, 2015

    Avago continues its acquisition spree. Broadcom (network chipsets and NPUs, CPUs, etc.). This is looking like a more integrated semiconductor IP play here. They grabbed LSI, and shed the non-chippery bits. They grabbed PLX. And Emulex. As they say, curiouser and curiouser. This makes perfect sense to me, and given the other acquisition announced today,… Read More »...


  • Team Verify's Blog

    Team Verify's Blog

    DVCon 2013 for Formal and ABV Users
    Published. February 11, 2013

    At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). However, Team Verify would like to alert users of Cadence Incisive formal and multi-engine tools, apps, and assertion-based verification (ABV) to the following papers and posters focused on this domain. * Session 2, Tuesday Feb. 26, 9-10:30am features two papers: Paper 2.1, "Overcoming AXI Asynchronous Bridge...


  • Robin Bornoff's Blog

    Robin Bornoff's Blog

    Xilinx Patent for Critical Tj Prediction
    Published. September 19, 2014

    A recently issued patent describes a process by which the critical IC temperature (junction temperature, Tj) can be determined in an end user environment. A critical junction temperature is one that, should the IC temperature go beyond it, will continue to increase in a thermal runaway scenario. In other words the environment in which the […]...


  • EDA Blog

    EDA Blog

    AVX Low-Profile MLO Diplexers Provide Advantages for Mobile Apps
    Published. January 14, 2014

    AVX 0603 and 0805 MLO Diplexers measure at less than 0.55 mm and provide low insertion loses, parasitics, and high heat dissipation for Wi-Fi, WiMax, mobile telecomm, and GPS applications. Read more: AVX Low-Profile MLO Diplexers Provide Advantages for Mobile AppsTwitter @edablog : : Jobs : : Embedded Star : : FPGA Blog : : […]...


  • EDA Blog

    EDA Blog

    AVX Low-Profile MLO Diplexers Provide Advantages for Mobile Apps
    Published. January 14, 2014

    AVX 0603 and 0805 MLO Diplexers measure at less than 0.55 mm and provide low insertion loses, parasitics, and high heat dissipation for Wi-Fi, WiMax, mobile telecomm, and GPS applications. Read more: AVX Low-Profile MLO Diplexers Provide Advantages for Mobile AppsTwitter @edablog : : Jobs : : Embedded Star : : FPGA Blog : : […]...


  • Conversation Central

    Conversation Central

    So you think verifying an FPGA is a piece of cake? Think again.
    Published. June 30, 2013

    Guest: Sheela Pillai, Director of Verification, Altera Host: Yvette Huygen, Director Worldwide Public Relations and Corporate Communications, Synopsys Inc. If your browser doesn’t support Flash, click here to download the show and play it locally. With the spotlight on increasing complexity of microprocessors and SoCs, it’s tempting to think that FPGA verification isn’t so difficult. […]...


  • Chris A. Ciufo on All Things Embedded

    Chris A. Ciufo on All Things Embedded

    Baby, You Can Drive (the PCIe clock in) My Car
    Published. May 2, 2014

    Among all the ARM-based media processors, Ethernet AVB networks, and Xilinx Zynq-based ADAS (advanced driver assistance system) safety features, it’s the humble PCI Express clock generator that really drives the car’s IVI systems. Continue reading →...


  • FPGA Blog

    FPGA Blog

    Pentek releases new Onyx family 3U VPX board, based on Xilinx Virtex-7 FPGA
    Published. May 1, 2014

    Pentek has announced the Model 52751, the newest addition to the Onyx family. The Model 52571 is a two-channel, wideband transceiver 3U VPX board, based on the Xilinx Virtex-7 FPGA. It is suitable for connection to HF or IF ports of communication or radar systems. Read more Pentek releases new Onyx family 3U VPX board, […]...


  • Gabe On EDA

    Gabe On EDA

    Accellera, Deeper Dive, Real Intent, Xilinx, Synopsys
    Published. February 28, 2014

    This week both Xilinx and Synopsys introduced new products. Xilinx is growing into a complete system company while Synopsys is benefitting from the acquired technology in hardware emulation to keep the competition in this sector very much alive. Taking advantage of the remote management capabilities built in all the latest computing platform, companies, not just governments, can now take a look at your activity on the web. So quit blaming the NSA alone, commercial reasons are an even bigger motivator...


  • Brian's Brain

    Brian's Brain

    Get a Head Start on Next-Generation 20 nm Designs
    Published. December 17, 2013

    Altera: Start designing today with Arria 10 FPGAs and SoCs, and experience the breakthrough capabilities not possible in previous midrange devices. Download Altera’s Quartus® II software Arria® 10 Edition v13.1, the first available software for 20 nm devices!...


  • Anablog

    Anablog

    Get a Head Start on Next-Generation 20 nm Designs
    Published. December 17, 2013

    Altera: Start designing today with Arria 10 FPGAs and SoCs, and experience the breakthrough capabilities not possible in previous midrange devices. Download Altera’s Quartus® II software Arria® 10 Edition v13.1, the first available software for 20 nm devices!...


  • Now Hear This!

    Now Hear This!

    Get a Head Start on Next-Generation 20 nm Designs
    Published. December 17, 2013

    Altera: Start designing today with Arria 10 FPGAs and SoCs, and experience the breakthrough capabilities not possible in previous midrange devices. Download Altera’s Quartus® II software Arria® 10 Edition v13.1, the first available software for 20 nm devices!...


  • Practical Chip Design

    Practical Chip Design

    Get a Head Start on Next-Generation 20 nm Designs
    Published. December 17, 2013

    Altera: Start designing today with Arria 10 FPGAs and SoCs, and experience the breakthrough capabilities not possible in previous midrange devices. Download Altera’s Quartus® II software Arria® 10 Edition v13.1, the first available software for 20 nm devices!...


  • Critical Links

    Critical Links

    Get a Head Start on Next-Generation 20 nm Designs
    Published. December 17, 2013

    Altera: Start designing today with Arria 10 FPGAs and SoCs, and experience the breakthrough capabilities not possible in previous midrange devices. Download Altera’s Quartus® II software Arria® 10 Edition v13.1, the first available software for 20 nm devices!...


  • EEBeat

    EEBeat

    Free conference Tuesday by Analog Devices – Xilinx – MathWorks
    Published. April 29, 2013

    by Jim Harrison The conference is in Santa Clara: Tuesday April 30, 2013 9am to 4:30pm Santa Clara Marriott Santa Clara, CA Analog Devices and event partners, Xilinx and MathWorks, invite you to a one-day conference featuring leading industry experts presenting complete signal processing solutions for a number of application areas chain, and system-ready solutions [...]...


  • Green Hills Software

    Green Hills Software

    Green Hills Software Announces INTEGRITY RTOS and MULTI IDE Support for Altera's Cyclone V SoC
    Published. April 23, 2013

    Integrated ARM-based Hard Processor System (HPS) Combined with FPGA Advances Reductions in System Power, Cost and Board Space...





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