FPGA & CPLD

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    Arteris Enhances Network-on-Chip Offerings to Address Full Range of SoC Designs

Featured White Papers

  • Demystifying DO-254

    Interest in DO-254 first occurred in Europe and has since spread to the US commercial aircraft industry. If you are being asked about your company’s DO-254 direction and compliance, but have been overwhelmed with information on the subject, then this article is for you.

  • Power Consumption at 40 and 45 nm

    At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection.

  • Accurately Analyzing Power in a Simulink Software Model-Based Design Flow

    Frequency, run time, and area utilizations are widely used as benchmarking metrics to gauge quality of results (QoR) for FPGA designs and tool performance.

  • Capabilities to Maximize Productivity for FPGA Debug and Verification

    Whether your task is to verify the functional correctness of a design, ensure adequate timing performance, or to quickly bring up a hardware platform in the lab environment, efficient verification and debug typically requires evaluating the design from multiple perspectives—ranging from high-level functional characteristics to low-level performance details—each at different phases of the design flow.

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