Driving the I2C bus with Next-Generation Buffers



While next-generation I2C buffer devices are good for putting the I2C control buses you already know to work, their true claim to fame could be how they assist with cost, power dissipation, and design complexity, helping system control architectures mature along with overall system design.

Over the past several decades, the Inter-Integrated Circuit (I2C) bus standard has been the dominant control bus standard for most electronic systems. I2C has a loyal following because of its ease of implementation, flexibility, and the large ecosystem of integrated circuits that support the standard. I2C’s ubiquity as the control interface of choice often drives device selection decisions, which in turn shape the overall system architecture.

“Not having pull-up resistors also avoids multiple points of possible system failure.”

System management buses like I2C have become important control points for differentiating designs through system software (firmware). Given the importance placed on system control buses like I2C, it’s crucial that you get the maximum benefit out of your I2C bus to help solve implementation issues and meet system design objectives.

You probably face a multitude of challenges when designing modern electronic-based systems. For example, keeping power dissipation to a minimum is often key for battery-powered systems, while for industrial systems power dissipation is directly connected to thermal performance.

An Opportunity to Reduce Cost
Another area where you’re likely challenged is in system build cost. Market-price competition often drives the need to reduce cost from one product generation to the next. Often, system cost is directly related to design complexity. Complex system designs mean more components, software, and engineering effort to design and test systems. Any opportunity to reduce system complexity is often an opportunity to reduce system cost.

A system’s I2C bus implementation can play a role in helping address cost, power, design complexity, and performance challenges. Next-generation I2C buffers break from traditional I2C implementations by offering a solution that can help you address modern system design issues while staying true to the I2C heritage that has made the standard so widely accepted.

With I2C buffers like TI’s TCA980x series, you can solve common I2C design issues such as level translation, bus buffering, and bus capacitive loading while also tackling system-level challenges such as power, cost, and complexity.

Several key features and characteristics help distinguish the new class of I2C devices from other I2C buffering solutions. For example, placing current-source drivers on the B-side port is a departure from the traditional voltage-based implementations found on virtually all I2C buffers and provides multiple benefits. The B-side bus lines do not need the pull-up resistors commonly used on traditional I2C implementations, and their elimination provides incremental system cost savings, especially for larger control bus implementations. Not having pull-up resistors also avoids multiple points of possible system failure.

Longer Battery Life
The TCA980x’s current-mode implementation means that the I2C bus operation will consume much lower power. Power consumption for the TCA980x is approximately 20 times lower than comparable voltage-mode devices (75μA vs. 1,500μA); see Figure 1. At a system level, lower power dissipation translates into longer battery life and much better thermal performance. The ability to improve battery life is likely to be one of the easiest ways that you can help achieve system design goals without having to compromise performance.

Figure 1: TCA980x vs traditional I2C buffer static current consumption comparison

Figure 1: TCA980x vs. traditional I2C buffer static current consumption comparison

I2C buffers also provide the added benefit of I2C-level translation, with support down to 0.8V. Support for 0.8V helps future-proof your I2C control bus designs as peripheral and processor input/output (I/O) voltages move lower over time. In addition, the flexibility to support device I/O voltages down to 0.8V gives you more options in signal-chain device selection.

Another common issue is having to tweak pull-up resistors to meet system timing parameters, especially rise time, for heavily loaded bus implementations. Figure 2 compares TCA980x rise-time performance vs. traditional pull-up-based I2C bus implementations. As you can see, for heavily loaded bus environments, current source-based buffer device designs have superior rise-time performance compared to traditional I2C buffers.

Figure 2: Rise-time performance of current-source driver vs. a traditional voltage/resistor approach

Figure 2: Rise-time performance of current-source driver vs. a traditional voltage/resistor approach

You can appreciate the combined benefits of the new I2C buffers when evaluating the benefits at a system level. System control and communication buses are essentially the central nervous systems of their respective applications. All too often, designers must compromise on the design of their control bus implementations, like not tweaking pull-up resistor values to save engineering time and cost.

Another area where designers often compromise is when optimizing the operating power consumption of the I2C control bus. The size and expanse of most I2C bus designs often requires more engineering time than you may have in your budget. New I2C buffers enable you to architect control buses that enable core system components to operate at their intended maximum level. Current source driver-based I2C buffers with their superior timing characteristics, lower operating current consumption and lower voltage support provide the functionality and performance needed to implement control buses from a system-level perspective.

Summary
Current source-based I2C buffer devices represent a modern approach to implementing I2C buses. With next-generation I2C buffer devices, you can not only implement I2C control buses that you are familiar with, but also address critical design targets such as cost, power dissipation and design complexity. You can implement system control architectures that evolve with the overall system design rather than being a bottleneck in the system design process.


Atul-Patel-HSAtul Patel is a Product Marketer and New Business Development Manager for industrial markets within TI’s Standard Logic Product Line. Patel has more than 20 years of systems and marketing experience with analog and mixed signal devices covering a broad spectrum of markets including Industrial, Automotive and Telecom. He has a Bachelor of Science degree in Computer Engineering as well as an MBA from the University of Central Florida.

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