The Power Challenge: How Low Can You Go?

Intel addresses designers’ power issues with new generations of Intel® Core™ processors, updated low-power Intel® Atom™ processors, and the new Intel® Quark™ processor core for SoCs targeted to the Internet of Things.

As more of our lives revolve around the use of mobile devices such as cell phones, tablets, laptop computers and assorted other devices (smart watches, mp3 and video players, cameras, game systems, other wearable products, etc.), low power consumption has become the mantra for every designer of the chips and final systems. Reducing the power consumption of the components used in the system as well as architecting the system for power efficiency are key challenges designers are facing with each new product generation. And this challenge is getting increasingly more difficult with each turn of the screw.

No company sees this challenge more than Intel, and over the last five years the company has addressed the power issue in several ways. First, with new generations of its mainstream Intel® Core™ i7/i5/i3 processors that operate at a fraction of the power of previous-generation processors; second, with its family of low-power Intel® Atom™ processors targeted at portable computing, embedded and consumer applications; and third, a new low-power Intel® Quark™ processor, designed for low-cost/low-power applications such as ASICs targeted at the “Internet-of-things.”

These solutions come as a response both to market demands as well as competition from its mainstream competitor, Advanced Micro Devices, which has also been working hard to reduce CPU power consumption. There are also well-entrenched IP suppliers such as ARM, MIPS (now part of Imagination Technology), Tensilica (now part of Cadence Design Systems) and several others, who all offer low-power processor cores targeted at the mobile device market, industrial systems, white goods and still other applications.

Although still not officially released, the Quark CPU core was developed by Intel for use in system-on-chip (SoC) solutions. The core is compatible with previous 32-bit Intel architecture CPUs such as the Pentium, but includes an enhanced instruction set and built-in security and manageability features which Intel feels makes it well-suited for the next wave of cost-effective, intelligent, connected devices. About one-fifth the area of the Atom processor core, the Quark core consumes about one-tenth the power of the Atom processor core, which can range from 180 mW to about 1.5 W depending on voltage and clock frequency.

One proposed SoC reference design using the Quark core running at 400 MHz is the SoC X1000—a chip that contains USB 2.0, Ethernet, SPI, I2C, a DDR3 DRAM controller with ECC support, 512 Mbytes of embedded SRAM, a PCIe port and many other I/O features. An AMBA bus fabric on the SoC provides a well-known, standard interface for designers to customize the SoC by adding their own intellectual property. The core is fully synthesizable and has an open architecture and an open ecosystem that will make it easy to integrate into the target system.

The fully-integrated voltage regulators on the 4th generation Intel® Core™ processors processor run at 140 MHz. That high operating frequency keeps the size of the inductors and capacitors to a minimum, allowing the inductors to be deposited as traces on the package, and the capacitors implemented as MIM structures on the chip.

The SoC has a thermal design point from 1.9 to 2.2 W depending on the internal voltage regulator setting, and can operate over a 0⁰C to 70 ⁰C commercial temperature range. Intel does plan on offering an extended temp range version capable of -40⁰C to +85 ⁰C operation that would allow the SoC to meet the requirements of industrial, medical and military systems. The SoC also comes with a software suite of interoperable security, manageability and connectivity utilities, and is supported by the Wind River Intelligent Device Platform, which provides operating system and middleware software stack.

Low-power processor cores such as the M0+ and M3+ from ARM have already established a yardstick by which other low-power processors try to measure up. The M0+ consumes just 9.8 µW/MHz when implemented in a 90-nm low-power process, while the M3 consumes 32 µW/MHz in the same process (and just 7 µW/MHz in a 40-nm process). And although the cores consume little power, once the ARM-based SoC design is completed, the total SoC power consumption is comparable to that of an Intel Quark processor-based SoC.

At the other end of the CPU spectrum, processors for desktop and server systems are also targets for power reduction. For example, at the 2014 International Solid-State Circuits Conference, Intel presented several papers on energy-efficient computing in which they demonstrated a 20x reduction in idle power for the 4th generation Intel Core processors, and techniques to get 10 hours of battery life and three weeks of standby on select Intel Atom and Intel Celeron processor SOCs (codename Bay Trail). Next-generation efficiency gains will come from innovative circuits, architecture improvements and I/O circuits that operate at lower voltages and adaptively scale performance.

There were many enhancements employed in the 4th generation Intel Coreprocessors to achieve higher performance while lowering the power consumption. One of the more unusual aspects of the design was the inclusion of up to 13 fully-integrated voltage regulators (FIVR)—synchronous buck-switching circuits that operate at 140 MHz (see figure). The high switching frequency allows the LC output filters to be small enough so they can be implemented on the CPU using package trace inductors, and in most cases, on-chip metal-insulator-metal (MIM) capacitors. The high current density of 32 A/mm2 requires a modest silicon area, which makes it an affordable option.

The 1.7 to 1.8 V input supply to the FIVR replaces multiple supply inputs used in the previous generation processors. The resulting reductions in platform area, cost and thickness enable thinner platforms with more features and larger batteries. Additionally, relaxed voltage specification on the input voltage lead to an order-of-magnitude reduction in decoupling, which allows the input rail to quickly ramp the input voltage off to save power and quickly ramp it back on to resume operation. This aspect of the processor operation accounts for nearly 50% of the gain in battery life.

At the conference, an energy-efficient graphics core fabricated in a 22 nm process leveraged adaptive clocking, selective boosting and a state-retentive sleep mode to lower power consumption. Adaptive clocking mitigates the impact of fast voltage droops, selective boosting allows low-voltage operation of embedded register files and ROM arrays, and the state retentive sleep mode can reduce leakage by a factor of 10. Additionally, the use of near-threshold voltage operation boosts the GFLOPS/W performance by 2.7 X compared to nominal operating voltage. Overall, these enhancements allow the graphics engine to deliver 1.4 X higher peak GFLOPS/W.

In its recently unveiled Intel Atom processor family, based on the Silvermont microarchitecture, Intel designers were able to craft a new low-power microarchitecture that delivers 3X the peak performance or 5X lower power at the same performance as the current generation Intel Atom processors. Fabricated in a 22 nm process, the processor has a wider dynamic operating range with enhanced active and idle power management. Additionally the core includes new instruction extensions and an out-of-order execution engine for more efficient program execution.

dave-bursky-crop2Dave Bursky, a contributing editor for Chip Design magazine, is also president of PRN Engineering, a technical writing and market consulting company. In addition to contributing to Chip Design magazine, he was the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an editor and engineer.

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