Deeper Dive – Intel’s 14nm – August 29, 2014



Intel remains coy on 14nm process details

Earlier this month, Intel announced details of the Core M processor microarchitecture, the first to be manufactured using 14nm.

Intel14nm-21August-300x224Intel’s 14nm manufacturing process and microarchitecture promises to bring high performance, low power capabilities to computing, from the cloud infrastructure and the Internet of Things, down to personal and mobile computing. Although more details will be announced next month at the developers’ forum in San Francisco (September 9 – 11), some people have got their hands on the Bradwell CPU and everyone has a view on the implications for performance and scalability.

Intel describes the 14nm process as the next step in the evolution of the processor, delivering “razor thin devices”, with taller fins (42nm, instead of the 34nm high fins, used in the 22nm process) and placed closer together to shrink the area and therefore wafer costs.

Second-generation Tri-gate, or FinFET, transistors contribute to a lower cost per transistor than the earlier 22nm mode. This is attributed to both area scaling and self-aligned, double-patterning lithography.

The fin pitch is 42nm, a reduction of 0.7x, compared to the company’s 22nm process. The gate pitch has been reduced 0.78x and is down to 70nm, which the interconnect pitch has been reduced 0.65x, to 52nm.

It has not all been plain sailing for Intel. Yield problems, caused by scaling the gate and fin pitches fairly aggressively, are reported to be the reason for a product delay, although Intel claims that it maintains a significant lead in the industry, shipping a second FinFET technology ahead of others. Mark Bohr, senior fellow, Technology and Manufacturing Group, director, Process Architecture and Integration insisted “the cost per transistor continues to come down”.

The main bone of contention for Zvi Or-Bach, president and CEO, MonolithIC 3D, is that the SRAM cell size, at 0.0588µm², although reduced from the 22nm technology, is not as small as it should be. “Yes, it is the smallest, published size for an SRAM bitcell,” he concedes, but “the 14nm node 6T SRAM size for conventional dimensional scaling should be 0.092 µm²,” he contests. “And if Intel can really scale more aggressively to compensate for the extra capital costs, then the 6T SRAM at 14nm should be about 0.03µm²m or even smaller,” he says.

Or-Bach also questions the 2x increase in transistor density, compared to 22nm, and refers to one of Intel’s own charts, which would confirm that some ‘spin’ has been put on the figures. Or-Bach concludes: “Actually, the basic transistor gate pitch indicates on a 1.64x increase in transistor density”.

Intel14nm-Broadwell_Package_Diagonal-i-300x231The first systems based on the Core M processor will be available at the end of this year, and available to OEMs in the first half of next year. The process and lead SoC are qualified and in volume production in the fabs in Orgeon and Arizona. The fab in Ireland is due to begin 14nm production in 2015.

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