Test Access versus Crowded PCBAs
The drive to smaller form factors, rising bus speeds and other pressures mean cramped quarters for PCBAs. And while denser and denser PCBAs can put the squeeze on test access, today there are test methodologies that break from the conventional to help maximize test coverage.
Electrical test, unlike imaging test, requires access and physical connection to the electronic circuit’s nets to provide the stimulus and measure the expected results. A test probe contacts a test pad of the net on a printed circuit board assembly (PCBA). Electrical test makes it possible to validate the electrical path of a net whether the trace and solder joint on the PCBA is visible or hidden—as for example with the ball grid array (BGA) or microBGA IC packages popular for SoCs.
Test access can be reduced as PCBA density increases to accommodate:
- Smaller (and smaller) form factors
- Less sockets as more devices are soldered down (CPU, Memory)
- IC package on IC package assembly
- Increasing bus speeds
- High density interconnect (HDI) for soldered down LPDDR3 memory
- Cost pressures
To recover test access, it’s now possible to use a methodology that specifies how test targets, or bead probes, can be placed directly onto copper signal traces. This approach yields superior test coverage by providing test access points virtually anywhere on a board layout. Selecting a test access technology that does not use traditional test pads offers the advantage of demanding negligible additional real estate. And the bead probes can be placed on high-speed traces without affecting signal fidelity.
Ultra Large Scale Integration Test Efficiency
IEEE 1149.1, commonly referred to as Boundary Scan, is a reliable test methodology to identify the IC package and validate the connectivity of the IC package to the PCBA. Boundary scan only requires test access to four pins of the IEEE 1149.1 test access port (TAP) regardless of the number of pins of the IC package. It is a very efficient and productive test methodology for ultra large scale integration (ULSI) devices like SoCs.
Boundary scan analyzers are available which have small footprints and maximize test coverage by using boundary scan test extensions. It’s also possible to test non-boundary scan devices by using devices which are boundary scan-enabled to act as drivers/receivers, doing away with the need for physical test access or nails.
Testing Intel® Microarchitecture-Based Processor Designs
Intel® Silicon View Technology (Intel® SVT), a proprietary test technology from Intel, enables the test for Broadwell CPU designs if test access is constrained by PCBA real estate or high-speed signal fidelity. It requires test access to the debug port2 and uses Intel® DFx abstraction layer to securely access the Broadwell CPU silicon to verify its function and that of surrounding devices.
Intel SVT requires the BIOS to be set up according to Intel’s BIOS Writer Guide3, reserving a designated register to host the results of the Intel SVT test. During manufacturing test, the PCBA under test has to be powered up safely to run the BIOS and Intel SVT will post the results of its test into the designated register. The content of the register is then compared to known good board values to assess whether the PCBA passes or fails the set of tests.
Intel SVT will test via the Broadwell CPU (and BIOS) the:
- Platform hub controller (PCH)
- Graphics, e.g., VGA, HDMI, eDP
- High-speed I/O (HSIO) e.g. PCIe, SATA, USB3
- Communication interfaces, e.g., LAN, USB2
- I/O peripherals, e.g., keyboard, audio
In-circuit test should be implemented for nets with available test access to ensure these nets are devoid of open and short and the components loaded are correct. Preferably these nets should include power and ground nets to increase the confidence of successfully sequencing power to the PCBA prior to Intel SVT test. Test-access-challenged designs should prioritize test access to the debug port, power and ground nets and critical components.
After completing the unpowered in-circuit test, advanced In-circuit testers (ICTs) or boundary scan analyzers can sequence the power to the Broadwell CPU PCBA and measure the on-board voltages. The ICT will shut off the power to protect the PCBA if the on-board voltages are not within the safe limits. After successfully powering up the PCBA, boundary scan tests will verify the solder joints of the CPU (and PCH in 2 chip designs). If an open or short is detected, the test will abort; otherwise it will continue to tests to validate the memory, sensor hub and high-speed bus using loop-back connectors.
At the completion of these tests, the ICT or x1149 will launch the Intel SVT tests using Intel DFx abstraction layer to verify the PCH, memory, graphics and HSIO (USB 3.0, SATA, PCIe,…) and peripherals.
At the conclusion of a successful combined ICT or x1149 with Intel SVT test, confidence will be high the CPU and peripherals on the motherboard are in good working condition, ready to be assembled into the final product. Figure 1 illustrates a Broadwell CPU design and the recommended test strategy with Intel SVT.
Author Mark Lau began his career as a field applications engineer and has taken on several roles in sales and business development within the electronic manufacturing test equipment business. Prior to joining Hewlett-Packard in 1993, he worked at Schlumberger Systems and GenRad.
He currently has a Product Marketing role focusing on new test technologies with Keysight’s Measurement Systems Division. MSD products include electronic manufacturing test equipment like In-Circuit Tester and Functional Testers.