Featured Blogs

• Chipnastics

  

  New Processor Core Options Try Some ARM Wrestling

  When designing a system on a chip (SoC) that employs one or more embedded processor cores, the choice...

• Editor's Note

  

  Moving Targets

  The future success of DVFS and near-threshold computing look dubious—at least for SoCs.

• JB’s Circuit

  

  Long Standards, Twinkie IP, Macro Trends, and Patent Trolls

  In Part II, IP Extreme’s Savage reveals why IP standards take so long while discussing brand values,...

• Chris A. Ciufo on All Things Embedded

  

  Intel vs GM: What’s In Store for Intel’s New CEO, President

  Today chip giant Intel announced outgoing CEO Paul Otellini’s replacement: he’s Brian Krzanich,...

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• My date picker  /  (Consumerization: BYOD)

  Hello, Whilst writing this I actually fixed the issue but I thought I'd post anyway as this technique might be useful to others... I have a javascript class I wrote (alas I can't post the whole code as the IP technically belongs to the company I work for) which presents ......

• DAC 2013 AMS Verification Luncheon: Advance Your Mixed-signal Verification Techniques to the Next Level  /  (Analog Insights)

    Well DAC 2013 is around the corner, so I guess it is time to blog about it, especially since this is in Austin And no, I am not going to tell you about the best BBQ joints or sushi places (yes I did say sushi in Texas) since I lived there for almost 15 [...]...

• Xilinx 7 Series FPGAs, Zynq-7000 SoCs Achieved Full PCI Express Compliance  /   (FPGA Blog)

  Xilinx’s All Programmable 7 series FPGAs and Zynq-7000 All Programmable SoCs have achieved full PCI Express compliance and are now listed on the PCI-SIG integrator’s list. With 7 series FPGA and Zynq-7000 All Programmable SoC integrated blocks for PCI Express Gen2 and Gen3, designers can meet high system bandwidth...

• Cadence Tempus Timing Signoff Solution Speeds Timing Closure  /   (EDA Blog)

  Cadence Design Systems announced the Tempus Timing Signoff Solution. The Tempus static timing analysis and closure tool enables System-on-Chip (SoC) developers to speed timing closure and move chip designs to fabrication quickly. The Cadence Tempus Timing Signoff Solution is expected to be available in the third quarter...

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