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DMP Adds High-End OpenGL ES 2.0 IP Cores and Multicore Configurations to Its SMAPH-S Product Family
May 7, 2012 -- Digital Media Professionals, Inc. (DMP), a provider of 2D/3D graphics intellectual property (IP) cores, today announced a significant product expansion to its scalable
PLDA Introduces QuickTCP - Full Hardware 10G TCP/IP Stack IP core for FPGA
New IPC Survey to Measure Impact of On-Shoring in the Electronics Industry
eMemory NeoBit Silicon IP to Play an Important Role in MEMS Applications
Microchip Announces 25% Performance Increase to dsPIC® DSCs for Digital-Power Applications
Microchip Introduces General-Purpose 8-bit PIC® Microcontrollers With Next-Generation Digital and Analog Peripherals
Microchip Upgrades Enhanced Core dsPIC33E and PIC24E Devices to 70 MIPS
Synopsys Announces DesignWare Embedded Memories and Logic Libraries for TSMC 28-nanometer Processes
VeriSilicon Licenses ZSP G3 Cores to Marvell
Arteris Counters Sonics Patent Infringement Claims
Featured Blogs
JB’s Circuit
Low-Power Undercurrents at GlobalPress 2012
While not the primary theme at this year’s Globalpress eSummit 2012, low power concerns were present...
Editor's Note
The move to the next few process nodes will have a big effect on power, performance and design....
Koby's Kaos
The sleigh is ready, the presents packed, it’s the futures I’m worried about. Less wires, more batteries,...
Discourse on Embedded Signal Processing
DSPBridge Open Source DSP Development On OMAP
The DSPBridge project allows open-source developers to use the OMAP processor’s on-chip DSP with...
Updating a design to modern concepts … / (scalability.org)
So in order to (really) bring my monitoring app into the modern age, I want to change its flow from a synchronous on-demand event driven analysis and reporting tool, to an asynchronous monitoring and analysis tool, with an on-demand “report” function which is basically a presentation core atop the data set....
Cadence Expands System and SoC Verification Offerings / (Gabe On EDA)
The pressure to improve the verificat5ion environment is growing. Very large designs enabled by continuous advances in semiconductors manufacturing as well as the acceptance of third party IP use has increased the difficulties faced by verification engineers. Recent product releases in the emulation and acceleration market,...
ISTEP 2012: MIC and the mechanics / (Soft Talk - Multicore and Parallel Programming )
Intel’s Many Integrated Core architecture (MIC, pronounced ‘Mike’) was a hot topic at this week’s Intel Software Conference, and I had a chance to find out how it works and how developers will be able to exploit it. If you’re not familiar with it, it’s an architecture that’s optimised for highly parallelised...
Lessons from CDNLive! India Best Paper -- Property Driven Simulation in IEV / (Team Verify's Blog)
Recently the CDNLive! India 2011 best paper award winner, "Complex IP Verification Methodology Using Property Driven Simulation in IEV," was published in TechOnline India. This is great news for the verification community because the techniques the NVidia authors describe have broad applications beyond the...
Featured Articles
Startup Packet Plus Rolls Embedded Debugger Tool
Seeking to boost development times and fill a void in the communications equipment market, startup Packet Plus Inc. has come out of stealth mode to introduce its first product: an interactive
FSA Promotes Innovation Through Global Collaboration and Dissemination of Valuable Industry Information
FSA, a leading semiconductor trade association, is the voice of the global fabless business model
Know the Key Aspects of IP Integration
The use of intellectual property (IP) in a 130-nm or below system-on-a-chip (SoC) is a common and
EECatalog on Facebook
Featured Product Briefs
ChipEstimate.com Chip Planning Portal
ChipEstimate.com provides design teams with the latest information on semiconductor IP
Designware Verification IP Solutions
Synopsys provides engineers with the broadest portfolio of Verification IP for the industry's most
True Circuits, Inc.
True Circuits' complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros
ASIC Design Services
Time to Market Inc. (TTM) is and ASIC Design Services Company providing ASIC design to leading
DesignWare Mixed Signal IP Solutions
Today's complex designs are quickly transitioning to high-speed interconnect standards, which are
Mentor Graphics IP Products Portfolio
Mentor Graphics® offers a variety of industry-leading, standards-based IP cores that are
Advanced Semiconductor IP
Virage Logic is a global leader in semiconductor IP platforms comprising embedded memories, logic
