What are the latest hot buttons for users integrating ARM-based microcontrollers? NXP Semiconductor’s (www.nxp.com) Rob Cosaro, systems architecture manager in charge of NXP’s ARM-based microcontroller architectures shares his thoughts on this issue during a recent interview with Low Power Systems Design Resource Catalog. Here’s what he had to say.

Ann Steffora Mutschler: What are the trends you are seeing right now in low power design?
Rob Cosaro: Our group does microcontrollers and what is driving low power design is mostly battery life in handheld applications. That’s a primary driver to have lower power microcontrollers. Also, low power design is being driven by applications where power consumption has to be non-intrusive or small compared to the application.

One specific area of applications is e-meters (energy-meters). E-metering is a big application area that requires low power design techniques, and in fact all meters need very low power because they want to be a non-intrusive power monitor.

Another application area is telemetry—things you want to monitor or measure that are not intrusive as well. For example, a solar power monitor where you don’t want to have big power consumption, but rather you want to measure the current or voltage of what the system is producing. Also for remote sensors or telemetry applications, where you are trying to measure something remotely in which you’d like to have the battery life last a long time, in-service requirements for the battery needs to be very low because you don’t want to have service technicians go out and replace them. Those can be industrial applications as well where you are monitoring things like vibration or temperature in remote locations in a factory, as an example.

There are also a lot of medical applications that require low power design. We are in a broad market and not particularly tied to one space so low power design is something that goes across a wide variety of spaces.

Ann Steffora Mutschler: What are some other applications in the industrial space that require low power design?
Rob Cosaro: There are industrial environments where temperature is important. It’s not just about the battery life but rise over the baseplate temperature. The more you dissipate, the more elevated the temperature is which requires bigger heat sinks. These are applications where the customer is trying to retrofit to allow for extra space, and lower power consumption makes it possible for them to add more functionality within given environmental parameters.

Ann Steffora Mutschler: Are there certain techniques that you use to address these things?
Rob Cosaro: Yes, although some are proprietary and have certain patent application ideas. One thing that’s pretty obvious is as we go down in process nodes, what happens is that the capacitance gets a lot less in the manufacturing process. Dynamic current is specified as ½ CV2F. C is the capacitance of the device, and this value is lowering, and because of geometries getting smaller, the voltage is lowering too (V2). We’re using state-of-the-art processes to reduce the dynamic current, but then there’s a trade-off. What happens is that the leakage current goes way up because as you lower the process node, the thresholds have to be at a certain point or you can’t get any operating frequency out of them so leakage current goes up. But there are some things we are doing to optimize those nodes by increasing thresholds because we don’t necessarily need to have the fT (maximum frequency) of the part – we want to operate at lower frequencies by taking advantage of the lower capacitance and lower voltages of those nodes. So we are trying to optimize the process for our particular devices that we’re making.

Another technique we use is breaking the problem into two parts: dynamic and static. Dynamic current, as stated above, is ½ CV2F. We can’t do much about the C except go down the different process nodes. The frequency, we can scale for the particular application but we still want to operate at the high frequencies too sometimes in order to do better processing by doing what is called “clock gating” to remove the clock from clocking all the time to all the stuff from within the part. It’s a common technique where architecturally, as an example, there’s a bunch of registers that are used to set up a peripheral and then they are not used after that, so why are we clocking those all the time? It’s wasting power. As a designer, you can go in and add clock gating techniques to those flip-flops that you know about, and that’s what we do to a large extent.

There are also things called “automatic clock gate insertion” by tools. Tool vendors have come up with their own ways to do this and it catches some things that we haven’t done by hand or visually. Those add another 10% reduction in dynamic power.

For leakage current, we can shut things off that we don’t need, so there are a bunch of voltage domains internally that we just turn things off. When we go into stand-by mode, we turn stuff off.

Those are the common technique. There are others, but I can’t comment on them, that are a little bit more aggressive and have interesting effects.

Ann Steffora Mutschler: What are customers asking for in terms of power consumption?
Rob Cosaro: One thing that we recognize is the fact that we have to be very efficient with our clocks that for every clock, we don’t waste clock cycles. In the processor core, we work closely with ARM – they are our primary supplier of cores. Working with them in conjunction with memory interfaces, we don’t have wait states; we try to minimize wait states. Every clock that’s used is used for processing.

Another issue is that a lot of times processors aren’t so good at doing bit manipulation and things like that. The processor has to turn on to do those things. What we’ve done in some cases is modify or change the peripherals in order to autonomously do things without the processor being involved.

Ann Steffora Mutschler is Editor of Extension Media’s EECatalog Resource Catalogs, and is also a Contributing Editor to Chip Design Magazine’s System-Level Design and Low-Power Design Communities. Her previous experience includes a long stint as a Senior Editor at Reed Business Information for publications including EDN, Electronic News and Electronic Business. She has moderated a number of panels in Silicon Valley and has written for publications worldwide.