Supported Architectures: 4-bit, 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, ARM, DSP, FPGAs, Freescale (Coldfire, MCORE, HC08 etc), MIPS, OMAP, Power Architecture™ (including PowerPC), Virage Memory, X86, XScale, Other
Compatible Operating Systems: Embedded Linux, Java-Embedded, Mentor Graphics/Nucleus, Windows Embedded

The Xilinx® CoolRunner™-II family provides the fastest, lowest cost and lowest power 1.8V CPLDs. CoolRunner-II CPLDs deliver the ultimate system solution enabling integration of discrete system functions into a single re-programmable device. Multiple device options offer a wide range of densities, abundant I/O, and the industry’s smallest form factor CPLD package to bring the benefits of programmable logic to high performance or portable applications.

CoolRunner-II CPLDs deliver true high performance and low power at the same time with the lowest standby current in the industry without the use of power down modes.

Revolutionary power-saving features include second-generation Fast Zero Power (FZP) process technology for the lowest standby current (as low as 12 µA), DataGATE signal blocking to stop unwanted input switching from continuously draining system power, and superior clock management capabilities that enhance performance while reducing clocking power. CoolRunner-II CPLDs are also unique in their ability to provide the fastest in-system programming and on-the-fly reconfiguration.

With such performance boosting and power reduction technologies, CoolRunner-II CPLDs enable systems designers to better differentiate their products from the competition, enhance the features of existing chipsets, and innovate with entirely new features to open new markets.

FEATURES & BENEFITS

• All-digital core and FZP process technology for ultra low power of 28.8 µW and 16 µA typical standby
• Up to 303 MHz performance with less than 100 µA standby current

• Supports 500mV input hysteresis for improved noise immunity, reduced power consumption, and superior signal integrity
• Multiple I/O standard support including LVTTL, LVCMOS, SSTL and HSTL for creating chip-to-chip and chip-to-memory interfaces

TECHNICAL SPECS

• Six device options with densities from 32 to 512 macrocells and multi-voltage I/O operation from 1.5V to 3.3V
• Available on industry-leading nonvolatile 0.18-micron CMOS process technology
• Wide package selection including fine pitch and Pb-free options
• Xilinx CPLD Design Kit provides everything needed to design and debug
• CoolRunner reference designs offer drop-in, ready-to-use functions provided in HDL design code

AVAILABILITY

Now

APPLICATION AREAS

Consumer, Wireless Communications, and Industrial, Scientific and Medical Instrumentation

Contact Information

Xilinx, Inc.

2100 Logic Drive
San Jose, CA, 95124
USA

tele: 408.559.7778
fax: 408.559.7114
more_info@xilinx.com
www.xilinx.com